Weixin Deng (邓伟信)
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This project is a RISC-V CPU with a 5-stage pipeline written in Verilog HDL, which is a course project of Computer Architecture, ACM Class @ SJTU.
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A toy RISC-V CPU, course project of Computer Architecture
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dengwxn/RISC-V-CPU
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A toy RISC-V CPU, course project of Computer Architecture
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