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Winch: v128 logical ops for x64 (bytecodealliance#10109)
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* v128.not

* v128.and

* v128.andnot

* v128.or

* rename test files

* v128.xor

* enable spec tests

* v128.bitselect

* v128.any_true

* v128.load*_lane

* v128.load*_lane

* cleanup duplicate methods

* move lane/load to wasm_store/load

* rename v128 functions

* ensure avx support

* fmt

* fix merge blips

* fix unsupported tests

* fix missing avx checks
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@MarinPostma
MarinPostma authored Jan 29, 2025
1 parent 24620d9 commit cb195e5
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Showing 23 changed files with 1,081 additions and 281 deletions.
26 changes: 13 additions & 13 deletions crates/wast-util/src/lib.rs
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Expand Up @@ -425,14 +425,9 @@ impl WastTest {
"misc_testsuite/simd/almost-extmul.wast",
"misc_testsuite/simd/canonicalize-nan.wast",
"misc_testsuite/simd/cvt-from-uint.wast",
"misc_testsuite/simd/issue4807.wast",
"misc_testsuite/simd/issue6725-no-egraph-panic.wast",
"misc_testsuite/simd/issue_3327_bnot_lowering.wast",
"misc_testsuite/simd/load_splat_out_of_bounds.wast",
"misc_testsuite/simd/unaligned-load.wast",
"multi-memory/simd_memory-multi.wast",
"spec_testsuite/simd_bit_shift.wast",
"spec_testsuite/simd_bitwise.wast",
"spec_testsuite/simd_boolean.wast",
"spec_testsuite/simd_const.wast",
"spec_testsuite/simd_conversions.wast",
Expand Down Expand Up @@ -472,16 +467,8 @@ impl WastTest {
"spec_testsuite/simd_int_to_int_extend.wast",
"spec_testsuite/simd_lane.wast",
"spec_testsuite/simd_load.wast",
"spec_testsuite/simd_load16_lane.wast",
"spec_testsuite/simd_load32_lane.wast",
"spec_testsuite/simd_load64_lane.wast",
"spec_testsuite/simd_load8_lane.wast",
"spec_testsuite/simd_load_zero.wast",
"spec_testsuite/simd_splat.wast",
"spec_testsuite/simd_store16_lane.wast",
"spec_testsuite/simd_store32_lane.wast",
"spec_testsuite/simd_store64_lane.wast",
"spec_testsuite/simd_store8_lane.wast",
];

if unsupported.iter().any(|part| self.path.ends_with(part)) {
Expand All @@ -499,6 +486,19 @@ impl WastTest {
"spec_testsuite/simd_align.wast",
"spec_testsuite/simd_load_extend.wast",
"spec_testsuite/simd_load_splat.wast",
"spec_testsuite/simd_store16_lane.wast",
"spec_testsuite/simd_store32_lane.wast",
"spec_testsuite/simd_store64_lane.wast",
"spec_testsuite/simd_store8_lane.wast",
"spec_testsuite/simd_load16_lane.wast",
"spec_testsuite/simd_load32_lane.wast",
"spec_testsuite/simd_load64_lane.wast",
"spec_testsuite/simd_load8_lane.wast",
"spec_testsuite/simd_bitwise.wast",
"misc_testsuite/simd/load_splat_out_of_bounds.wast",
"misc_testsuite/simd/unaligned-load.wast",
"multi-memory/simd_memory-multi.wast",
"misc_testsuite/simd/issue4807.wast",
];

if unsupported.iter().any(|part| self.path.ends_with(part)) {
Expand Down
32 changes: 32 additions & 0 deletions tests/disas/winch/x64/v128_ops/and.wat
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@@ -0,0 +1,32 @@
;;! target = "x86_64"
;;! test = "winch"
;;! flags = [ "-Ccranelift-has-avx" ]

(module
(func (export "_start") (result v128)
(v128.and
(v128.const i64x2 0 0xFFFFFFFFFFFFFFFF)
(v128.const i64x2 0xFFFFFFFFFFFFFFFF 0)
)))
;; wasm[0]::function[0]:
;; pushq %rbp
;; movq %rsp, %rbp
;; movq 8(%rdi), %r11
;; movq 0x10(%r11), %r11
;; addq $0x10, %r11
;; cmpq %rsp, %r11
;; ja 0x4a
;; 1c: movq %rdi, %r14
;; subq $0x10, %rsp
;; movq %rdi, 8(%rsp)
;; movq %rsi, (%rsp)
;; movdqu 0x1c(%rip), %xmm0
;; movdqu 0x24(%rip), %xmm1
;; vpand %xmm0, %xmm1, %xmm1
;; movdqa %xmm1, %xmm0
;; addq $0x10, %rsp
;; popq %rbp
;; retq
;; 4a: ud2
;; 4c: addb %al, (%rax)
;; 4e: addb %al, (%rax)
32 changes: 32 additions & 0 deletions tests/disas/winch/x64/v128_ops/andnot.wat
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@@ -0,0 +1,32 @@
;;! target = "x86_64"
;;! test = "winch"
;;! flags = [ "-Ccranelift-has-avx" ]

(module
(func (export "_start") (result v128)
(v128.andnot
(v128.const i64x2 0 0xFFFFFFFFFFFFFFFF)
(v128.const i64x2 0xFFFFFFFFFFFFFFFF 0)
)))
;; wasm[0]::function[0]:
;; pushq %rbp
;; movq %rsp, %rbp
;; movq 8(%rdi), %r11
;; movq 0x10(%r11), %r11
;; addq $0x10, %r11
;; cmpq %rsp, %r11
;; ja 0x4a
;; 1c: movq %rdi, %r14
;; subq $0x10, %rsp
;; movq %rdi, 8(%rsp)
;; movq %rsi, (%rsp)
;; movdqu 0x1c(%rip), %xmm0
;; movdqu 0x24(%rip), %xmm1
;; vpandn %xmm1, %xmm0, %xmm1
;; movdqa %xmm1, %xmm0
;; addq $0x10, %rsp
;; popq %rbp
;; retq
;; 4a: ud2
;; 4c: addb %al, (%rax)
;; 4e: addb %al, (%rax)
36 changes: 36 additions & 0 deletions tests/disas/winch/x64/v128_ops/any_true.wat
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@@ -0,0 +1,36 @@
;;! target = "x86_64"
;;! test = "winch"
;;! flags = [ "-Ccranelift-has-avx" ]

(module
(func (export "_start") (result i32)
(v128.any_true
(v128.const i64x2 0 0xFFFFFFFFFFFFFFFF)
)))
;; wasm[0]::function[0]:
;; pushq %rbp
;; movq %rsp, %rbp
;; movq 8(%rdi), %r11
;; movq 0x10(%r11), %r11
;; addq $0x10, %r11
;; cmpq %rsp, %r11
;; ja 0x48
;; 1c: movq %rdi, %r14
;; subq $0x10, %rsp
;; movq %rdi, 8(%rsp)
;; movq %rsi, (%rsp)
;; movdqu 0x1c(%rip), %xmm0
;; vptest %xmm0, %xmm0
;; movl $0, %eax
;; setne %al
;; addq $0x10, %rsp
;; popq %rbp
;; retq
;; 48: ud2
;; 4a: addb %al, (%rax)
;; 4c: addb %al, (%rax)
;; 4e: addb %al, (%rax)
;; 50: addb %al, (%rax)
;; 52: addb %al, (%rax)
;; 54: addb %al, (%rax)
;; 56: addb %al, (%rax)
36 changes: 36 additions & 0 deletions tests/disas/winch/x64/v128_ops/bitselect.wat
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@@ -0,0 +1,36 @@
;;! target = "x86_64"
;;! test = "winch"
;;! flags = [ "-Ccranelift-has-avx" ]

(module
(func (export "_start") (result v128)
(v128.bitselect
(v128.const i64x2 0x3298472837385628 0x58212382347A3994)
(v128.const i64x2 0x7483929592465832 0x1285837491823847)
(v128.const i64x2 0xFFFFFF0FFFFFFFFF 0xFFFFFF0FFFFFFFFF)
)))
;; wasm[0]::function[0]:
;; pushq %rbp
;; movq %rsp, %rbp
;; movq 8(%rdi), %r11
;; movq 0x10(%r11), %r11
;; addq $0x10, %r11
;; cmpq %rsp, %r11
;; ja 0x5a
;; 1c: movq %rdi, %r14
;; subq $0x10, %rsp
;; movq %rdi, 8(%rsp)
;; movq %rsi, (%rsp)
;; movdqu 0x2c(%rip), %xmm0
;; movdqu 0x34(%rip), %xmm1
;; movdqu 0x3c(%rip), %xmm2
;; vpand %xmm0, %xmm2, %xmm15
;; vpandn %xmm1, %xmm0, %xmm3
;; vpor %xmm3, %xmm15, %xmm3
;; movdqa %xmm3, %xmm0
;; addq $0x10, %rsp
;; popq %rbp
;; retq
;; 5a: ud2
;; 5c: addb %al, (%rax)
;; 5e: addb %al, (%rax)
39 changes: 39 additions & 0 deletions tests/disas/winch/x64/v128_ops/load_lane/load16.wat
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@@ -0,0 +1,39 @@
;;! target = "x86_64"
;;! test = "winch"
;;! flags = [ "-Ccranelift-has-avx" ]

(module
(memory 1 1)
(func (export "_start") (result v128)
(v128.load16_lane
1 (i32.const 0) (v128.const i64x2 0xFFFFFFFFFFFFFFFF 0xFFFFFFFFFFFFFFFF)
)))
;; wasm[0]::function[0]:
;; pushq %rbp
;; movq %rsp, %rbp
;; movq 8(%rdi), %r11
;; movq 0x10(%r11), %r11
;; addq $0x10, %r11
;; cmpq %rsp, %r11
;; ja 0x50
;; 1c: movq %rdi, %r14
;; subq $0x10, %rsp
;; movq %rdi, 8(%rsp)
;; movq %rsi, (%rsp)
;; movdqu 0x2c(%rip), %xmm0
;; movl $0, %eax
;; movq 0x50(%r14), %rcx
;; addq %rax, %rcx
;; movzwq (%rcx), %r11
;; vpinsrw $1, %r11d, %xmm0, %xmm0
;; addq $0x10, %rsp
;; popq %rbp
;; retq
;; 50: ud2
;; 52: addb %al, (%rax)
;; 54: addb %al, (%rax)
;; 56: addb %al, (%rax)
;; 58: addb %al, (%rax)
;; 5a: addb %al, (%rax)
;; 5c: addb %al, (%rax)
;; 5e: addb %al, (%rax)
40 changes: 40 additions & 0 deletions tests/disas/winch/x64/v128_ops/load_lane/load32.wat
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@@ -0,0 +1,40 @@
;;! target = "x86_64"
;;! test = "winch"
;;! flags = [ "-Ccranelift-has-avx" ]

(module
(memory 1 1)
(func (export "_start") (result v128)
(v128.load32_lane
1 (i32.const 0) (v128.const i64x2 0xFFFFFFFFFFFFFFFF 0xFFFFFFFFFFFFFFFF)
)))
;; wasm[0]::function[0]:
;; pushq %rbp
;; movq %rsp, %rbp
;; movq 8(%rdi), %r11
;; movq 0x10(%r11), %r11
;; addq $0x10, %r11
;; cmpq %rsp, %r11
;; ja 0x4f
;; 1c: movq %rdi, %r14
;; subq $0x10, %rsp
;; movq %rdi, 8(%rsp)
;; movq %rsi, (%rsp)
;; movdqu 0x2c(%rip), %xmm0
;; movl $0, %eax
;; movq 0x50(%r14), %rcx
;; addq %rax, %rcx
;; movl (%rcx), %r11d
;; vpinsrd $1, %r11d, %xmm0, %xmm0
;; addq $0x10, %rsp
;; popq %rbp
;; retq
;; 4f: ud2
;; 51: addb %al, (%rax)
;; 53: addb %al, (%rax)
;; 55: addb %al, (%rax)
;; 57: addb %al, (%rax)
;; 59: addb %al, (%rax)
;; 5b: addb %al, (%rax)
;; 5d: addb %al, (%rax)
;; 5f: addb %bh, %bh
40 changes: 40 additions & 0 deletions tests/disas/winch/x64/v128_ops/load_lane/load64.wat
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@@ -0,0 +1,40 @@
;;! target = "x86_64"
;;! test = "winch"
;;! flags = [ "-Ccranelift-has-avx" ]

(module
(memory 1 1)
(func (export "_start") (result v128)
(v128.load64_lane
1 (i32.const 0) (v128.const i64x2 0xFFFFFFFFFFFFFFFF 0xFFFFFFFFFFFFFFFF)
)))
;; wasm[0]::function[0]:
;; pushq %rbp
;; movq %rsp, %rbp
;; movq 8(%rdi), %r11
;; movq 0x10(%r11), %r11
;; addq $0x10, %r11
;; cmpq %rsp, %r11
;; ja 0x4f
;; 1c: movq %rdi, %r14
;; subq $0x10, %rsp
;; movq %rdi, 8(%rsp)
;; movq %rsi, (%rsp)
;; movdqu 0x2c(%rip), %xmm0
;; movl $0, %eax
;; movq 0x50(%r14), %rcx
;; addq %rax, %rcx
;; movq (%rcx), %r11
;; vpinsrq $1, %r11, %xmm0, %xmm0
;; addq $0x10, %rsp
;; popq %rbp
;; retq
;; 4f: ud2
;; 51: addb %al, (%rax)
;; 53: addb %al, (%rax)
;; 55: addb %al, (%rax)
;; 57: addb %al, (%rax)
;; 59: addb %al, (%rax)
;; 5b: addb %al, (%rax)
;; 5d: addb %al, (%rax)
;; 5f: addb %bh, %bh
39 changes: 39 additions & 0 deletions tests/disas/winch/x64/v128_ops/load_lane/load8.wat
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@@ -0,0 +1,39 @@
;;! target = "x86_64"
;;! test = "winch"
;;! flags = [ "-Ccranelift-has-avx" ]

(module
(memory 1 1)
(func (export "_start") (result v128)
(v128.load8_lane
1 (i32.const 0) (v128.const i64x2 0xFFFFFFFFFFFFFFFF 0xFFFFFFFFFFFFFFFF)
)))
;; wasm[0]::function[0]:
;; pushq %rbp
;; movq %rsp, %rbp
;; movq 8(%rdi), %r11
;; movq 0x10(%r11), %r11
;; addq $0x10, %r11
;; cmpq %rsp, %r11
;; ja 0x50
;; 1c: movq %rdi, %r14
;; subq $0x10, %rsp
;; movq %rdi, 8(%rsp)
;; movq %rsi, (%rsp)
;; movdqu 0x2c(%rip), %xmm0
;; movl $0, %eax
;; movq 0x50(%r14), %rcx
;; addq %rax, %rcx
;; movzbq (%rcx), %r11
;; vpinsrb $1, %r11d, %xmm0, %xmm0
;; addq $0x10, %rsp
;; popq %rbp
;; retq
;; 50: ud2
;; 52: addb %al, (%rax)
;; 54: addb %al, (%rax)
;; 56: addb %al, (%rax)
;; 58: addb %al, (%rax)
;; 5a: addb %al, (%rax)
;; 5c: addb %al, (%rax)
;; 5e: addb %al, (%rax)
32 changes: 32 additions & 0 deletions tests/disas/winch/x64/v128_ops/not.wat
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@@ -0,0 +1,32 @@
;;! target = "x86_64"
;;! test = "winch"
;;! flags = [ "-Ccranelift-has-avx" ]

(module
(func (export "_start") (result v128)
(v128.not (v128.const i64x2 0xFFFFFFFFFFFFFFFF 0))))
;; wasm[0]::function[0]:
;; pushq %rbp
;; movq %rsp, %rbp
;; movq 8(%rdi), %r11
;; movq 0x10(%r11), %r11
;; addq $0x10, %r11
;; cmpq %rsp, %r11
;; ja 0x43
;; 1c: movq %rdi, %r14
;; subq $0x10, %rsp
;; movq %rdi, 8(%rsp)
;; movq %rsi, (%rsp)
;; movdqu 0x1c(%rip), %xmm0
;; vpcmpeqd %xmm15, %xmm15, %xmm15
;; vpxor %xmm0, %xmm15, %xmm0
;; addq $0x10, %rsp
;; popq %rbp
;; retq
;; 43: ud2
;; 45: addb %al, (%rax)
;; 47: addb %al, (%rax)
;; 49: addb %al, (%rax)
;; 4b: addb %al, (%rax)
;; 4d: addb %al, (%rax)
;; 4f: addb %bh, %bh
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