Skip to content

Commit

Permalink
Fix a few bugs
Browse files Browse the repository at this point in the history
  • Loading branch information
SingleAccretion committed Oct 27, 2023
1 parent f839217 commit 4a7c1e8
Show file tree
Hide file tree
Showing 4 changed files with 35 additions and 13 deletions.
7 changes: 3 additions & 4 deletions src/coreclr/jit/codegenarm64.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -4864,12 +4864,11 @@ void CodeGen::genCodeForJumpCompare(GenTreeOpCC* tree)

if (tree->OperIs(GT_JTEST))
{
ssize_t compareImm = op2->AsIntCon()->IconValue();

assert(isPow2(((size_t)compareImm)));
uint64_t compareImm = op2->AsIntCon()->IntegralValueUnsigned();
assert(isPow2(compareImm));

instruction ins = (cc.GetCode() == GenCondition::EQ) ? INS_tbz : INS_tbnz;
int imm = genLog2((size_t)compareImm);
int imm = genLog2(compareImm);

GetEmitter()->emitIns_J_R_I(ins, attr, compiler->compCurBB->GetJumpDest(), reg, imm);
}
Expand Down
2 changes: 1 addition & 1 deletion src/coreclr/jit/gentree.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -5122,7 +5122,7 @@ unsigned Compiler::gtSetEvalOrder(GenTree* tree)
{
GenTreeIntCon* con = tree->AsIntCon();
bool iconNeedsReloc = con->ImmedValNeedsReloc(this);
INT64 imm = con->LngValue();
INT64 imm = con->IntegralValue();
emitAttr size = EA_SIZE(emitActualTypeSize(tree));

if (iconNeedsReloc)
Expand Down
36 changes: 30 additions & 6 deletions src/coreclr/jit/gentree.h
Original file line number Diff line number Diff line change
Expand Up @@ -3120,6 +3120,22 @@ struct GenTreeIntCon : public GenTree
m_value = value;
}

uint64_t IntegralValueUnsigned() const
{
return Is32BitConst() ? static_cast<uint32_t>(m_value) : m_value;
}

void SetIntegralValueUnsigned(uint64_t value)
{
if (Is32BitConst())
{
assert(FitsIn<uint32_t>(value));
value = static_cast<int32_t>(value);
}

m_value = value;
}

//------------------------------------------------------------------------
// SetValueTruncating: Set the value, truncating to TYP_INT if necessary.
//
Expand Down Expand Up @@ -3148,14 +3164,12 @@ struct GenTreeIntCon : public GenTree
static_assert_no_msg(
(std::is_same<T, int32_t>::value || std::is_same<T, int64_t>::value || std::is_same<T, ssize_t>::value));

if (TypeIs(TYP_LONG))
if (Is32BitConst())
{
SetLngValue(value);
}
else
{
SetIconValue(static_cast<int32_t>(value));
value = static_cast<int32_t>(value);
}

SetIntegralValue(value);
}

int LoVal() const
Expand All @@ -3178,6 +3192,16 @@ struct GenTreeIntCon : public GenTree
bool FitsInAddrBase(Compiler* comp);
bool AddrNeedsReloc(Compiler* comp);
#endif

private:
bool Is32BitConst() const
{
#ifdef TARGET_64BIT
return TypeIs(TYP_INT);
#else
return !TypeIs(TYP_LONG);
#endif
}
};

// node representing a read from a physical register
Expand Down
3 changes: 1 addition & 2 deletions src/coreclr/jit/lower.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -3832,8 +3832,7 @@ GenTree* Lowering::LowerJTrue(GenTreeOp* jtrue)
newOper = GT_JTEST;
cc = cond->OperIs(GT_LT) ? GenCondition(GenCondition::NE) : GenCondition(GenCondition::EQ);
// x < 0 => (x & signBit) != 0. Update the constant to be the sign bit.
relopOp2->AsIntCon()->SetIntegralValue(
(static_cast<INT64>(1) << (8 * genTypeSize(genActualType(relopOp1)) - 1)));
relopOp2->AsIntCon()->SetIntegralValueUnsigned(1ULL << (8 * genTypeSize(genActualType(relopOp1)) - 1));
}
else if (cond->OperIs(GT_TEST_EQ, GT_TEST_NE) && isPow2(relopOp2->AsIntCon()->IconValue()))
{
Expand Down

0 comments on commit 4a7c1e8

Please sign in to comment.