[LoongArch64] Synchronize with PR#102592. (#102711)

* Fix the build error for LA64.
dotnet · May 28, 2024 · 8f2f3da · 8f2f3da
1 parent 9daa4b4
commit 8f2f3da
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Showing 2 changed files with 11 additions and 9 deletions.
diff --git a/src/coreclr/jit/lsrabuild.cpp b/src/coreclr/jit/lsrabuild.cpp
@@ -3303,7 +3303,7 @@ void LinearScan::BuildDefWithKills(GenTree* tree, int dstCount, SingleTypeRegSet
     }
 #endif // TARGET_64BIT
 }
-#endif // defined(TARGET_ARMARCH) || defined(TARGET_RISCV64)
+#endif // defined(TARGET_ARMARCH) || defined(TARGET_RISCV64) || defined(TARGET_LOONGARCH64)
 
 //------------------------------------------------------------------------
 // BuildCallDefsWithKills: Build one or more RefTypeDef RefPositions for the given node,

diff --git a/src/coreclr/jit/lsraloongarch64.cpp b/src/coreclr/jit/lsraloongarch64.cpp
@@ -681,7 +681,7 @@ int LinearScan::BuildCall(GenTreeCall* call)
 {
     bool                  hasMultiRegRetVal   = false;
     const ReturnTypeDesc* retTypeDesc         = nullptr;
-    regMaskTP             singleDstCandidates = RBM_NONE;
+    SingleTypeRegSet      singleDstCandidates = RBM_NONE;
 
     int srcCount = 0;
     int dstCount = 0;
@@ -700,8 +700,8 @@ int LinearScan::BuildCall(GenTreeCall* call)
         }
     }
 
-    GenTree*  ctrlExpr           = call->gtControlExpr;
-    regMaskTP ctrlExprCandidates = RBM_NONE;
+    GenTree*         ctrlExpr           = call->gtControlExpr;
+    SingleTypeRegSet ctrlExprCandidates = RBM_NONE;
     if (call->gtCallType == CT_INDIRECT)
     {
         // either gtControlExpr != null or gtCallAddr != null.
@@ -731,7 +731,7 @@ int LinearScan::BuildCall(GenTreeCall* call)
     {
         // For R2R and VSD we have stub address in REG_R2R_INDIRECT_PARAM
         // and will load call address into the temp register from this register.
-        regMaskTP candidates = RBM_NONE;
+        SingleTypeRegSet candidates = RBM_NONE;
         if (call->IsFastTailCall())
         {
             candidates = (allRegs(TYP_INT) & (RBM_INT_CALLEE_TRASH & ~RBM_GSCOOKIE_TMP));
@@ -994,14 +994,16 @@ int LinearScan::BuildPutArgSplit(GenTreePutArgSplit* argNode)
     // Registers for split argument corresponds to source
     int dstCount = argNode->gtNumRegs;
 
-    regNumber argReg  = argNode->GetRegNum();
-    regMaskTP argMask = RBM_NONE;
+    regNumber        argReg  = argNode->GetRegNum();
+    SingleTypeRegSet argMask = RBM_NONE;
     for (unsigned i = 0; i < argNode->gtNumRegs; i++)
     {
         regNumber thisArgReg = (regNumber)((unsigned)argReg + i);
         argMask |= genRegMask(thisArgReg);
         argNode->SetRegNumByIdx(thisArgReg, i);
     }
+    assert((argMask == RBM_NONE) || ((argMask & availableIntRegs) != RBM_NONE) ||
+           ((argMask & availableFloatRegs) != RBM_NONE));
 
     if (putArgChild->OperGet() == GT_FIELD_LIST)
     {
@@ -1023,7 +1025,7 @@ int LinearScan::BuildPutArgSplit(GenTreePutArgSplit* argNode)
 
             // Consume all the registers, setting the appropriate register mask for the ones that
             // go into registers.
-            regMaskTP sourceMask = RBM_NONE;
+            SingleTypeRegSet sourceMask = RBM_NONE;
             if (sourceRegCount < argNode->gtNumRegs)
             {
                 sourceMask = genRegMask((regNumber)((unsigned)argReg + sourceRegCount));
@@ -1138,7 +1140,7 @@ int LinearScan::BuildBlockStore(GenTreeBlk* blkNode)
                 // We don't need to materialize the struct size but we still need
                 // a temporary register to perform the sequence of loads and stores.
                 // We can't use the special Write Barrier registers, so exclude them from the mask
-                regMaskTP internalIntCandidates =
+                SingleTypeRegSet internalIntCandidates =
                     allRegs(TYP_INT) & ~(RBM_WRITE_BARRIER_DST_BYREF | RBM_WRITE_BARRIER_SRC_BYREF);
                 buildInternalIntRegisterDefForNode(blkNode, internalIntCandidates);