Further cleanup.

dotnet · Mar 29, 2023 · b3f5200 · b3f5200
1 parent 9a5bd0d
commit b3f5200
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Showing 7 changed files with 55 additions and 109 deletions.
diff --git a/src/coreclr/jit/codegen.h b/src/coreclr/jit/codegen.h
@@ -952,7 +952,6 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
                                          regNumber                 baseReg,
                                          regNumber                 offsReg,
                                          HWIntrinsicSwitchCaseBody emitSwCase);
-    instruction genMask2VectorIns(var_types baseType);
 #endif // defined(TARGET_XARCH)
 
 #ifdef TARGET_ARM64

diff --git a/src/coreclr/jit/emitxarch.cpp b/src/coreclr/jit/emitxarch.cpp
@@ -253,9 +253,7 @@ bool emitter::IsDstSrcSrcAVXInstruction(instruction ins) const
     return (flags & INS_Flags_IsDstSrcSrcAVXInstruction) != 0;
 }
 
-// Returns true if the AVX instruction requires 3 operands and writes result
-// to mask register.
-bool emitter::IsThreeOperandInstructionMask(instruction ins) const
+bool emitter::IsThreeOperandAVXInstruction(instruction ins) const
 {
     if (!UseSimdEncoding())
     {
@@ -18227,7 +18225,7 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
         case INS_vpmovd2m:
         case INS_vpmovq2m:
         {
-            result.insLatency += PERFSCORE_LATENCY_1C;
+            result.insLatency += PERFSCORE_LATENCY_3C;
             result.insThroughput = PERFSCORE_THROUGHPUT_1C;
             break;
         }
@@ -18246,7 +18244,6 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
             break;
         }
 
-        // TODO-AVX512-XARCH double check
         case INS_vpcmpb:
         case INS_vpcmpw:
         case INS_vpcmpd:
@@ -18256,14 +18253,18 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
         case INS_vpcmpud:
         case INS_vpcmpuq:
         {
-            result.insLatency += PERFSCORE_LATENCY_3C;
+            result.insLatency += PERFSCORE_LATENCY_4C;
             result.insThroughput = PERFSCORE_THROUGHPUT_1C;
             break;
         }
 
-        // TODO-AVX512-XARCH double check
         case INS_vpmovm2b:
         case INS_vpmovm2w:
+        {
+            result.insLatency += PERFSCORE_LATENCY_3C;
+            result.insThroughput = PERFSCORE_THROUGHPUT_1C;
+            break;
+        }
         case INS_vpmovm2d:
         case INS_vpmovm2q:
         {

diff --git a/src/coreclr/jit/emitxarch.h b/src/coreclr/jit/emitxarch.h
@@ -402,7 +402,7 @@ void SetContains256bitOrMoreAVX(bool value)
 
 bool IsDstDstSrcAVXInstruction(instruction ins) const;
 bool IsDstSrcSrcAVXInstruction(instruction ins) const;
-bool IsThreeOperandInstructionMask(instruction ins) const;
+bool IsThreeOperandAVXInstruction(instruction ins) const;
 static bool HasRegularWideForm(instruction ins);
 static bool HasRegularWideImmediateForm(instruction ins);
 static bool DoesWriteZeroFlag(instruction ins);
@@ -414,13 +414,6 @@ static bool IsRexW1Instruction(instruction ins);
 static bool IsRexWXInstruction(instruction ins);
 static bool IsRexW1EvexInstruction(instruction ins);
 
-bool IsThreeOperandAVXInstruction(instruction ins)
-{
-    return (IsDstDstSrcAVXInstruction(ins) || IsDstSrcSrcAVXInstruction(ins) ||
-            (ins == INS_vpcmpb || ins == INS_vpcmpw || ins == INS_vpcmpd || ins == INS_vpcmpq || ins == INS_vpcmpub ||
-             ins == INS_vpcmpuw || ins == INS_vpcmpud || ins == INS_vpcmpuq));
-}
-
 bool isAvxBlendv(instruction ins)
 {
     return ins == INS_vblendvps || ins == INS_vblendvpd || ins == INS_vpblendvb;

diff --git a/src/coreclr/jit/hwintrinsiccodegenxarch.cpp b/src/coreclr/jit/hwintrinsiccodegenxarch.cpp
@@ -2153,39 +2153,4 @@ void CodeGen::genX86SerializeIntrinsic(GenTreeHWIntrinsic* node)
     genProduceReg(node);
 }
 
-//------------------------------------------------------------------------
-// genX86SerializeIntrinsic: Generate an "vpmovm2t" instruction, where t
-// represents a byte, word, dword, or qword, from a JIT base type.
-//
-// Operation takes a AVX512 mask register and populates a SIMD register
-// elementwise with 0s or 1s based on the associated bit in the mask register.
-//
-// Arguments:
-//    node - base JIT type
-//
-instruction CodeGen::genMask2VectorIns(var_types baseType)
-{
-    switch (baseType)
-    {
-        case TYP_BYTE:
-        case TYP_UBYTE:
-            return INS_vpmovm2b;
-        case TYP_SHORT:
-        case TYP_USHORT:
-            return INS_vpmovm2w;
-        case TYP_INT:
-        case TYP_UINT:
-        case TYP_FLOAT:
-            return INS_vpmovm2d;
-        case TYP_LONG:
-        case TYP_ULONG:
-        case TYP_DOUBLE:
-            return INS_vpmovm2q;
-        default:
-            unreached();
-    }
-
-    return INS_invalid;
-}
-
 #endif // FEATURE_HW_INTRINSICS
diff --git a/src/coreclr/jit/hwintrinsicxarch.cpp b/src/coreclr/jit/hwintrinsicxarch.cpp
@@ -1346,6 +1346,7 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic        intrinsic,
 
         case NI_Vector128_Equals:
         case NI_Vector256_Equals:
+        case NI_Vector512_Equals:
         {
             assert(sig->numArgs == 2);
 
@@ -1360,20 +1361,6 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic        intrinsic,
             break;
         }
 
-        // TODO-XARCH-AVX512 see how to merge this into below
-        case NI_Vector512_Equals:
-        {
-            assert(sig->numArgs == 2);
-            assert(IsBaselineVector512IsaSupportedDebugOnly());
-
-            var_types simdType = getSIMDTypeForSize(simdSize);
-            op2 = impSIMDPopStack(simdType);
-            op1 = impSIMDPopStack(simdType);
-            retNode = gtNewSimdCmpOpNode(GT_EQ, retType, op1, op2, simdBaseJitType, simdSize,
-                                             /* isSimdAsHWIntrinsic */ false);
-            break;
-        }
-
         case NI_Vector512_EqualsAll:
         case NI_Vector512_op_Equality:
         {

diff --git a/src/coreclr/jit/instr.h b/src/coreclr/jit/instr.h
@@ -141,7 +141,8 @@ enum insFlags : uint64_t
     // Avx
     INS_Flags_IsDstDstSrcAVXInstruction = 1ULL << 25,
     INS_Flags_IsDstSrcSrcAVXInstruction = 1ULL << 26,
-    INS_Flags_Is3OperandInstructionMask = 1ULL << 27,
+    INS_Flags_IsMskSrcSrcEvexInstruction = 1ULL << 27,
+    INS_Flags_Is3OperandInstructionMask = (INS_Flags_IsDstDstSrcAVXInstruction | INS_Flags_IsDstSrcSrcAVXInstruction | INS_Flags_IsMskSrcSrcEvexInstruction),
 
     // w and s bits
     INS_FLAGS_Has_Wbit = 1ULL << 28,