[RISC-V] Replace rsGetRsvdReg with ordinary temp registers (#95317)

* [RISC-V] Replace rsGetRsvdReg calls in emitInsTernary with ordinary temps

* [RISC-V] Give emitInsTernary a haircut

* [RISC-V] Add missing newline when printf is exceeds MAX_LEN

* [RISC-V] Replace rsGetRsvdReg with a normal constant in genLcLHeap. Plus a small optimization, fuse addi+and into andi to avoid using a temp reg.

* [RISC-V] Replace rsGetRsvdReg with ordinary temp regs in GT_(MOD|DIV|MULHI)

* [RISC-V] Replace rsGetRsvdReg with ordinary temp reg in switch tables

* [RISC-V] Replace rsGetRsvdReg with ordinary temps in genCodeForCompare

* [RISC-V] Replace rsGetRsvdReg with ordinary temps in genCodeForShift

* [RISC-V] Replace rsGetRsvdReg with ordinary temp reg in genCodeForIndexAddr and genLeaInstruction

* [RISC-V] Replace rsGetRsvdReg with ordinary temp reg in genIntCastOverflowCheck

* [RISC-V] Code review: remove an always true if and don't enter divisor checking when we know we need a temp

* [RISC-V] Small refactorings after review

src/coreclr/jit/codegen.h

@@ -800,7 +800,11 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
     void genSetRegToCond(regNumber dstReg, GenTree* tree);
 
 #if defined(TARGET_ARMARCH) || defined(TARGET_LOONGARCH64) || defined(TARGET_RISCV64)
-    void genScaledAdd(emitAttr attr, regNumber targetReg, regNumber baseReg, regNumber indexReg, int scale);
+    void genScaledAdd(emitAttr  attr,
+                      regNumber targetReg,
+                      regNumber baseReg,
+                      regNumber indexReg,
+                      int scale RISCV64_ARG(regNumber scaleTempReg));
 #endif // TARGET_ARMARCH || TARGET_LOONGARCH64 || TARGET_RISCV64
 
 #if defined(TARGET_ARMARCH)
@@ -817,6 +821,7 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
     // Generate the instruction to move a value between register files
     void genBitCast(var_types targetType, regNumber targetReg, var_types srcType, regNumber srcReg);
 
+public:
     struct GenIntCastDesc
     {
         enum CheckKind
@@ -894,6 +899,7 @@ XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
         }
     };
 
+protected:
     void genIntCastOverflowCheck(GenTreeCast* cast, const GenIntCastDesc& desc, regNumber reg);
     void genIntToIntCast(GenTreeCast* cast);
     void genFloatToFloatCast(GenTree* treeNode);