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AVX10.1 API introduction in JIT #101938
AVX10.1 API introduction in JIT #101938
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Note regarding the
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch |
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CC. @dotnet/jit-contrib PR from Intel is ready for review and needs secondary sign-off. I've given this a decently thorough review already and plan on giving it one more pass before sign-off, but it could definitely do with another pair of eyes. |
@EgorBo please review the PR for AVX10.1. |
src/coreclr/jit/importercalls.cpp
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retNode = | ||
gtNewSimdHWIntrinsicNode(TYP_SIMD16, op1, op2, op3, NI_FMA_MultiplyAddScalar, callJitType, 16); | ||
GenTree* op3 = gtNewSimdCreateScalarUnsafeNode(TYP_SIMD16, impPopStack().val, callJitType, 16); |
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why do we remove impImplicitR4orR8Cast
from here?
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Looks like a merge error when rebasing. cleared it up to what it was.
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I think the RyuJIT side is ok with the Tanner's comments. Do we want to run some ISA outerloops?
Any idea why this PR causes big diffs on an Intel cpu (must be some Skylake/Cascade Lake cpu on Azure): MihuBot/runtime-utils#403 ? I presume it's supposed to be no-op |
Something is off here. We are not inlining the Vector512 method in some of these and resorting to software fallback |
There is a bug in there re ordering of flags being set. It got introduced when we added _EVEX flag. Will add a fix today |
…rmatting adn resolve errors introduced when merging with main
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@EgorBo I have pushed a fix and here are the diffs |
This PR tracks addition of AVX10.1 APIs in libraries along with relevant template tests and intrinsics in JIT. It also captures usage of the new intrinsics in JIT during lowering.