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Arm64/Sve: Remove unwanted insScalableOpts and instructions #103620

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merged 10 commits into from
Jun 18, 2024
Merged

Arm64/Sve: Remove unwanted insScalableOpts and instructions #103620

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60925bc
Fix AV in GatherVector
kunalspathak Jun 18, 2024
b766817
Remove INS_SCALABLE_OPTS_UNPREDICATED
kunalspathak Jun 18, 2024
04797f1
Remove INS_SCALABLE_OPTS_UNPREDICATED_WIDE
kunalspathak Jun 18, 2024
4b949be
TO_PREDICATE AND TO_VECTOR
kunalspathak Jun 18, 2024
f3ebe4d
Remove INS_SCALABLE_OPTS_BROADCAST
kunalspathak Jun 18, 2024
6c0cae0
Remove ins_sve_ldr_mask and ins_sve_str_mask
kunalspathak Jun 18, 2024
a395a9d
bug fix
kunalspathak Jun 18, 2024
08efeae
jit format
kunalspathak Jun 18, 2024
a1861d2
proper handling of OperIsMemoryLoad() for Gather APIs
kunalspathak Jun 18, 2024
3a30048
review comments
kunalspathak Jun 18, 2024
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483 changes: 208 additions & 275 deletions src/coreclr/jit/codegenarm64test.cpp
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70 changes: 7 additions & 63 deletions src/coreclr/jit/emitarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -4252,8 +4252,7 @@ void emitter::emitIns_Mov(
{
if (isPredicateRegister(dstReg) && isPredicateRegister(srcReg))
{
assert(insOptsNone(opt));

assert((opt == INS_OPTS_SCALABLE_B) || insOptsNone(opt));
opt = INS_OPTS_SCALABLE_B;
attr = EA_SCALABLE;

Expand Down Expand Up @@ -7882,42 +7881,14 @@ void emitter::emitIns_R_S(instruction ins, emitAttr attr, regNumber reg1, int va

case INS_sve_ldr:
{
assert(isVectorRegister(reg1));
isSimple = false;
size = EA_SCALABLE;
attr = size;
fmt = IF_SVE_IE_2A;

// TODO-SVE: Don't assume 128bit vectors
scale = NaturalScale_helper(EA_16BYTE);
ssize_t mask = (1 << scale) - 1; // the mask of low bits that must be zero to encode the immediate

if (((imm & mask) == 0) && (isValidSimm<9>(imm >> scale)))
{
imm >>= scale; // The immediate is scaled by the size of the ld/st
}
else
{
useRegForImm = true;
regNumber rsvdReg = codeGen->rsGetRsvdReg();
codeGen->instGen_Set_Reg_To_Imm(EA_PTRSIZE, rsvdReg, imm);
}
}
break;

// TODO-SVE: Fold into INS_sve_ldr once REG_V0 and REG_P0 are distinct
case INS_sve_ldr_mask:
{
assert(isPredicateRegister(reg1));
isSimple = false;
size = EA_SCALABLE;
attr = size;
fmt = IF_SVE_ID_2A;
ins = INS_sve_ldr;
fmt = isVectorRegister(reg1) ? IF_SVE_IE_2A : IF_SVE_ID_2A;

// TODO-SVE: Don't assume 128bit vectors
// Predicate size is vector length / 8
scale = NaturalScale_helper(EA_2BYTE);
scale = NaturalScale_helper(isVectorRegister(reg1) ? EA_16BYTE : EA_2BYTE);
ssize_t mask = (1 << scale) - 1; // the mask of low bits that must be zero to encode the immediate

if (((imm & mask) == 0) && (isValidSimm<9>(imm >> scale)))
Expand All @@ -7930,8 +7901,8 @@ void emitter::emitIns_R_S(instruction ins, emitAttr attr, regNumber reg1, int va
regNumber rsvdReg = codeGen->rsGetRsvdReg();
codeGen->instGen_Set_Reg_To_Imm(EA_PTRSIZE, rsvdReg, imm);
}
break;
}
break;

default:
NYI("emitIns_R_S"); // FP locals?
Expand Down Expand Up @@ -8161,42 +8132,14 @@ void emitter::emitIns_S_R(instruction ins, emitAttr attr, regNumber reg1, int va

case INS_sve_str:
{
assert(isVectorRegister(reg1));
isSimple = false;
size = EA_SCALABLE;
attr = size;
fmt = IF_SVE_JH_2A;

// TODO-SVE: Don't assume 128bit vectors
scale = NaturalScale_helper(EA_16BYTE);
ssize_t mask = (1 << scale) - 1; // the mask of low bits that must be zero to encode the immediate

if (((imm & mask) == 0) && (isValidSimm<9>(imm >> scale)))
{
imm >>= scale; // The immediate is scaled by the size of the ld/st
}
else
{
useRegForImm = true;
regNumber rsvdReg = codeGen->rsGetRsvdReg();
codeGen->instGen_Set_Reg_To_Imm(EA_PTRSIZE, rsvdReg, imm);
}
}
break;

// TODO-SVE: Fold into INS_sve_str once REG_V0 and REG_P0 are distinct
case INS_sve_str_mask:
{
assert(isPredicateRegister(reg1));
isSimple = false;
size = EA_SCALABLE;
attr = size;
fmt = IF_SVE_JG_2A;
ins = INS_sve_str;
fmt = isVectorRegister(reg1) ? IF_SVE_JH_2A : IF_SVE_JG_2A;

// TODO-SVE: Don't assume 128bit vectors
// Predicate size is vector length / 8
scale = NaturalScale_helper(EA_2BYTE);
scale = NaturalScale_helper(isVectorRegister(reg1) ? EA_16BYTE : EA_2BYTE);
ssize_t mask = (1 << scale) - 1; // the mask of low bits that must be zero to encode the immediate

if (((imm & mask) == 0) && (isValidSimm<9>(imm >> scale)))
Expand All @@ -8209,6 +8152,7 @@ void emitter::emitIns_S_R(instruction ins, emitAttr attr, regNumber reg1, int va
regNumber rsvdReg = codeGen->rsGetRsvdReg();
codeGen->instGen_Set_Reg_To_Imm(EA_PTRSIZE, rsvdReg, imm);
}
break;
}
break;

Expand Down
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