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Handle a missing case in zero-extend peephole #55129

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Jul 10, 2021
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7 changes: 7 additions & 0 deletions src/coreclr/jit/emitxarch.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -296,6 +296,13 @@ bool emitter::AreUpper32BitsZero(regNumber reg)
return false;
}

#ifdef TARGET_AMD64
if (id->idIns() == INS_movsxd)
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This code in general seems error prone given we've introduced a number of non-general purpose instructions (such as BMI1/BMI2) that operate on general purpose registers.

It might be good to log an issue and add a flag to the instruction table indicating whether or not the upper bits are zeroed for a given instruction.

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I think this should only be a problem for instructions with mixed operand sizes. Do any of the BMI instructions mix operand sizes?

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Sorry, this looks to have tagged the wrong line.

I meant AreUpper32BitsZero defaulting to true for any instruction with a "supported format" which deals with a 4-byte size: https://github.com/dotnet/runtime/pull/55129/files/f058b59c7eea2d743d728dc080613e8b6c710e61#diff-6b4e0f32449f2f144e05699f59f74415a564693637f643084a896dfbd081830dR313

// Else rely on operation size.
return (id->idOpSize() == EA_4BYTE);

This is basically assuming that any instruction that has a 4BYTE op size zeroes the upper bits and this isn't strictly true for every instruction. I expect its mostly correct due to most machines having the VEX encoding and due to most GPR instructions on 64-bit zeroing the upper bits for the 32-bit version, but it would also be nice if we had this explicitly codified (such as via an instruction flag).

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I do believe that check is right, at least from the perspective of the Intel manual. 3.4.1.1 of the volume on Basic Architecture states:

When in 64-bit mode, operand size determines the number of valid bits in the destination general-purpose
register:
• 64-bit operands generate a 64-bit result in the destination general-purpose register.
• 32-bit operands generate a 32-bit result, zero-extended to a 64-bit result in the destination general-purpose
register.
• 8-bit and 16-bit operands generate an 8-bit or 16-bit result. The upper 56 bits or 48 bits (respectively) of the
destination general-purpose register are not modified by the operation. If the result of an 8-bit or 16-bit
operation is intended for 64-bit address calculation, explicitly sign-extend the register to the full 64-bits.

Perhaps it's more that we get the operand size wrong for these instructions, or that we should have something representing the "destination operand size".

{
return false;
}
#endif

// movzx always zeroes the upper 32 bits.
if (id->idIns() == INS_movzx)
{
Expand Down
101 changes: 101 additions & 0 deletions src/tests/JIT/Regression/JitBlue/Runtime_55129/Runtime_55129.cs
Original file line number Diff line number Diff line change
@@ -0,0 +1,101 @@
// Licensed to the .NET Foundation under one or more agreements.
// The .NET Foundation licenses this file to you under the MIT license.

using System.Runtime.CompilerServices;

public class Runtime_55129
{
public static int Main()
{
int result = 100;
if (!Runtime_55129_1.Run())
result |= 1;
if (!Runtime_55129_2.Run())
result |= 2;
return result;
}
}

// These tests failed because of a missing zero extension because a peephole
// did not handle that 'movsxd' would sign extend.
public class Runtime_55129_1
{
static I s_i = new C();
static short s_7;
static sbyte[][] s_10 = new sbyte[][]{new sbyte[]{-1}};
[MethodImpl(MethodImplOptions.NoInlining)]
public static bool Run()
{
var vr59 = (uint)M6(s_10[0][0]);
return (long)vr59 == uint.MaxValue;
}

static ulong M6(sbyte arg0)
{
return (ulong)arg0;
ref short var1 = ref s_7;
s_i.Foo(var1);
}
}

interface I
{
void Foo<T>(T val);
}

class C : I
{
public void Foo<T>(T val) { }
}

struct S0
{
public long F5;
public S0(int f0, byte f1, ulong f2, byte f3, uint f4, long f5, int f6, int f7) : this()
{
}
}

class C0
{
public long F0;
}

class C1
{
public ulong F1;
}

public class Runtime_55129_2
{
static int[] s_2 = new int[] { -1 };
static C0 s_4 = new C0();
static S0 s_5;
static C1[][] s_47 = new C1[][] { new C1[] { new C1() } };
static bool s_result;
[MethodImpl(MethodImplOptions.NoInlining)]
public static bool Run()
{
s_5.F5 = s_2[0];
C1 vr4 = s_47[0][0];
var vr6 = vr4.F1;
M6(vr6);
return s_result;
}

static void M6(ulong arg0)
{
arg0 >>= 0;
if (-1 < (uint)(0U | M7(ref s_4.F0, new S0[][,] { new S0[,] { { new S0(-10, 1, 0, 178, 1671790506U, -2L, 1, -2147483648) } }, new S0[,] { { new S0(1330389305, 255, 1297834355652867458UL, 0, 1777203966U, 4402572156859115751L, -1597826478, 1) } }, new S0[,] { { new S0(2147483646, 15, 18446744073709551614UL, 9, 1089668776U, 8629324174561266356L, 2124906017, -1883510008) } } }, 1, new sbyte[] { -37, -21, 0, 0, 0, 0 }, new S0[] { new S0(219671235, 22, 11763641210444381762UL, 0, 2568868236U, -7432636731544997849L, 1623417447, -479936755), new S0(-2147483647, 108, 0, 1, 4294967294U, 9223372036854775807L, 539462011, 1), new S0(1, 0, 15733997012901423027UL, 212, 4294967294U, 4663434921694141184L, -2147483647, 1196938120), new S0(1, 68, 0, 14, 653907833U, -6962955672558660864L, 1966270988, -378944819) })))
{
s_result = true;
}
}

static short M7(ref long arg0, S0[][,] arg1, ushort arg2, sbyte[] arg3, S0[] arg4)
{
long vr20 = s_5.F5;
return (short)vr20;
}
}

Original file line number Diff line number Diff line change
@@ -0,0 +1,10 @@
<Project Sdk="Microsoft.NET.Sdk">
<PropertyGroup>
<OutputType>Exe</OutputType>
<DebugType>None</DebugType>
<Optimize>True</Optimize>
</PropertyGroup>
<ItemGroup>
<Compile Include="$(MSBuildProjectName).cs" />
</ItemGroup>
</Project>