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Adding support for X86Base.Pause() and ArmBase.Yield() #61065

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merged 4 commits into from
Nov 15, 2021

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tannergooding
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This resolves #53532

@dotnet-issue-labeler dotnet-issue-labeler bot added area-CodeGen-coreclr CLR JIT compiler in src/coreclr/src/jit and related components such as SuperPMI new-api-needs-documentation labels Nov 1, 2021
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Note regarding the new-api-needs-documentation label:

This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, to please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change.

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ghost commented Nov 1, 2021

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Issue Details

This resolves #53532

Author: tannergooding
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area-CodeGen-coreclr, new-api-needs-documentation

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@@ -16011,6 +16011,13 @@ emitter::insExecutionCharacteristics emitter::getInsExecutionCharacteristics(ins
result.insThroughput = PERFSCORE_THROUGHPUT_2X;
break;

case INS_pause:
{
result.insLatency = PERFSCORE_LATENCY_140C;
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it's 14x lower on pre-Skylakes. It reminds me this issue #8744

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Yes, but all of our latencies are currently dependent on and configured for Skylake.

We'd need some more advanced setup if we wanted to track per architecture latencies/throughput.

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I assume this is no-diff change?

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I assume this is no-diff change?

Correct, although it looks like there is some minor issue on Arm64 I might need to fix still.

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@echesakovMSFT, could you take a quick peak at the one additional commit that resolves the ARM64 issue.

It's now generating the correct code and working as expected. The issue was that the category wasn't being handled correctly and a few tweaks were needed to handle there being no args, no base type, and no EA_ATTR.

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The last change LGTM.

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Introduce pause intrinsics in order to support spin wait loop indication
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