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Optimization on LinearScan::buildPhysRegRecords #83862
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Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch, @kunalspathak Issue Detailsintroducing separate macro on higher 16 zmm registers and lower 16 zmm registers, skipping non-AVX512 register if AVX512 not available.
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@dotnet-policy-service agree company="Intel Corporation" |
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some tests failed, but it seems not to be caused by the changes in this PR. |
Failure is unrelated and being handled by #84012 |
fix the offset value when allocating upper registers, it should be the length of the lower register group.
@tannergooding Hi, is there anything further we need to do? Or this PR is ready to be merged. |
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LGTM
It seems the TP regression shows up because helix machines has EVEX encoding and this PR adds the extra check for it? @tannergooding - is that the right conclusion?
Thanks all! |
introducing separate macro on upper 16 zmm registers and lower 16 zmm registers, skipping upper 16 registers unless on 64-bit system.