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Expose AVX512 variants of SSE-SSE4.2 instructions #84909
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…lyHigh for AVX512F, AVX512BW, AVX512DQ, and AVX512DQ.VL
…etic, ShiftRightLogical, and ShiftRightLogical128BitLane for Avx512F, Avx512F.VL, and Avx512BW
Note regarding the This serves as a reminder for when your PR is modifying a ref *.cs file and adding/modifying public APIs, please make sure the API implementation in the src *.cs file is documented with triple slash comments, so the PR reviewers can sign off that change. |
Tagging subscribers to this area: @JulieLeeMSFT, @jakobbotsch, @kunalspathak Issue DetailsThis exposes 512-bit variants of all the relevant SSE-SSE4.2 instructions making progress towards completing:
For a few instructions, there is a new The breakdown of the changes are:
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CC. @dotnet/avx512-contrib, @dotnet/jit-contrib, @dotnet/area-system-runtime-intrinsics |
We see a TP improvement of
Linux shows a couple regressions in some of the "recursive implementations" for the Avx.Shuffle and Avx2.AlignRight APIs. Such diffs come from us supporting containment where we didn't previously and that hoisting the load into the jump table fallback. We can/should probably avoid containment in the case we need to generate such a jump table, but its a pre-existing condition for all such nodes, so we can handle it in a follow up PR (#84933). |
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JIT and BCL changes LGTM, I skimmed through the tests and they also look ok
Tests are passing, but timing out. I have up #84948 to try and help solve some of that. |
src/tests/JIT/HardwareIntrinsics/X86/Avx1/Avx1_handwritten_r.csproj
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src/tests/JIT/HardwareIntrinsics/X86/Avx1/Avx1_handwritten_r.csproj
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src/tests/JIT/HardwareIntrinsics/X86/Avx2/Avx2_handwritten_r.csproj
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if (Avx512BW.IsSupported) | ||
{ | ||
using (TestTable<short> intTable = new TestTable<short>(new short[32] { 1, -5, 100, 0, 1, 2, 3, 4, 1, -5, 100, 0, 1, 2, 3, 4, 1, -5, 100, 0, 1, 2, 3, 4, 1, -5, 100, 0, 1, 2, 3, 4 }, new short[32])) |
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using (TestTable<short> intTable = new TestTable<short>(new short[32] { 1, -5, 100, 0, 1, 2, 3, 4, 1, -5, 100, 0, 1, 2, 3, 4, 1, -5, 100, 0, 1, 2, 3, 4, 1, -5, 100, 0, 1, 2, 3, 4 }, new short[32])) | |
using (TestTable<short> intTable = new(new short[32] { 1, -5, 100, 0, 1, 2, 3, 4, 1, -5, 100, 0, 1, 2, 3, 4, 1, -5, 100, 0, 1, 2, 3, 4, 1, -5, 100, 0, 1, 2, 3, 4 }, new short[32])) |
a bit more terse; here and elsewhere
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This is setup in a way that makes it easier to switch to generated from a template in the future.
src/tests/JIT/HardwareIntrinsics/X86/Avx512DQ_VL_Vector128/Program.Avx512DQ_VL_Vector128.cs
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src/tests/JIT/HardwareIntrinsics/X86/Avx512F/ConvertToVector512Double.Int32.cs
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src/tests/JIT/HardwareIntrinsics/X86/Avx512F/ConvertToVector512Double.Single.cs
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src/tests/JIT/HardwareIntrinsics/X86/Avx512F/ConvertToVector512Double.Int32.cs
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src/tests/JIT/HardwareIntrinsics/X86/Avx512F_VL_Vector256/Program.Avx512F_VL_Vector256.cs
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src/tests/JIT/HardwareIntrinsics/X86/Avx512F/LoadAlignedVector512NonTemporal.cs
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LGTM pending green CI
Resolved merge conflicts. Should pass now that the tests are properly getting filtered and last run showed OSX got past the timeouts, etc. |
This exposes 512-bit variants of all the relevant SSE-SSE4.2 instructions making progress towards completing:
For a few instructions, there is a new
Q
variant of the instruction that supports 64-bit elements. Where relevant, existing code paths were updated to utilize this instructionThe breakdown of the changes are:
*.PlatformNotSupported.cs
version of the file*.cs
and*.PlatformNotSupported.cs
)