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[Mono] Intrinsify Vector128.Create on Arm64 for mini JIT #85404

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merged 3 commits into from
Apr 28, 2023
Merged

[Mono] Intrinsify Vector128.Create on Arm64 for mini JIT #85404

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0a0d8ad
Intrinsify Vector128.Create
fanyang-mono Apr 26, 2023
49cffbd
Hopefully fix the test failure
fanyang-mono Apr 27, 2023
3cb4c0a
Increase maximal instruction length
fanyang-mono Apr 28, 2023
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4 changes: 2 additions & 2 deletions src/mono/mono/mini/cpu-arm64.mdesc
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Original file line number Diff line number Diff line change
Expand Up @@ -525,8 +525,8 @@ insert_i1: dest:x src1:x src2:i len:8
insert_i2: dest:x src1:x src2:i len:8
insert_i4: dest:x src1:x src2:i len:8
insert_i8: dest:x src1:x src2:i len:8
insert_r4: dest:x src1:x src2:f len:8
insert_r8: dest:x src1:x src2:f len:8
insert_r4: dest:x src1:x src2:f len:12
insert_r8: dest:x src1:x src2:f len:12
create_scalar_int: dest:x src1:i len:8
create_scalar_float: dest:x src1:f len:12
create_scalar_unsafe_int: dest:x src1:i len:4
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19 changes: 14 additions & 5 deletions src/mono/mono/mini/mini-arm64.c
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Original file line number Diff line number Diff line change
Expand Up @@ -3944,10 +3944,19 @@ mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
break;
}

if (dreg != sreg1)
arm_neon_mov (code, dreg, sreg1);

arm_neon_ins_e(code, t, dreg, sreg2, ins->inst_c0, 0);
if (dreg != sreg1) {
if (dreg != sreg2) {
arm_neon_mov (code, dreg, sreg1);
arm_neon_ins_e(code, t, dreg, sreg2, ins->inst_c0, 0);
} else {
arm_neon_mov (code, NEON_TMP_REG, sreg1);
arm_neon_ins_e(code, t, NEON_TMP_REG, sreg2, ins->inst_c0, 0);
arm_neon_mov (code, dreg, NEON_TMP_REG);
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}
} else {
g_assert (dreg != sreg2);
arm_neon_ins_e(code, t, dreg, sreg2, ins->inst_c0, 0);
}
break;
}
case OP_ARM64_XTN:
Expand Down Expand Up @@ -4041,7 +4050,7 @@ mono_arch_output_basic_block (MonoCompile *cfg, MonoBasicBlock *bb)
}
break;
}
// Enable this when adding support for Narrow and enable support for Create at the same time
// This requires Vector64 SIMD support
// case OP_XCONCAT:
// arm_neon_ext_16b(code, dreg, sreg1, sreg2, 8);
// break;
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12 changes: 7 additions & 5 deletions src/mono/mono/mini/simd-intrinsics.c
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Expand Up @@ -1349,12 +1349,8 @@ emit_sri_vector (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsi
if (!(!strcmp (m_class_get_name (cmethod->klass), "Vector128") || !strcmp (m_class_get_name (cmethod->klass), "Vector")))
return NULL;
switch (id) {
case SN_Create:
case SN_GetLower:
case SN_GetUpper:
case SN_Shuffle:
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These were removed as well, as SN_Shuffle hasn't been supported by LLVM either. SN_ToVector128 and SN_ToVector128Unsafe were Vector64 API's and didn't apply to Vector128.

case SN_ToVector128:
case SN_ToVector128Unsafe:
return NULL;
default:
break;
Expand Down Expand Up @@ -1569,8 +1565,14 @@ emit_sri_vector (MonoCompile *cfg, MonoMethod *cmethod, MonoMethodSignature *fsi
MonoInst* ins = emit_simd_ins (cfg, klass, type_to_expand_op (etype->type), args [0]->dreg, -1);
ins->inst_c1 = arg0_type;
return ins;
} else if (is_create_from_half_vectors_overload (fsig))
} else if (is_create_from_half_vectors_overload (fsig)) {
#if defined(TARGET_ARM64)
// Require Vector64 SIMD support
if (!COMPILE_LLVM (cfg))
return NULL;
#endif
return emit_simd_ins (cfg, klass, OP_XCONCAT, args [0]->dreg, args [1]->dreg);
}
else if (is_elementwise_create_overload (fsig, etype))
return emit_vector_create_elementwise (cfg, fsig, fsig->ret, arg0_type, args);
break;
Expand Down