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Add arm64 encodings for IF_SVE_CL_3A to IF_SVE_CU_3A #95514

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Dec 4, 2023
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Add arm64 encodings for IF_SVE_CL_3A to IF_SVE_CU_3A #95514

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b56c574
Add arm64 encodings for IF_SVE_CL_3A to IF_SVE_CU_3A
a74nh Nov 29, 2023
da59654
Revert wsp printing
a74nh Dec 4, 2023
8d74718
Fix up sizes for WITH_SIMD_VECTOR instructions
a74nh Dec 4, 2023
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130 changes: 100 additions & 30 deletions src/coreclr/jit/codegenarm64.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -10195,22 +10195,22 @@ void CodeGen::genArm64EmitterUnitTests()

// IF_SVE_CN_3A
theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_2BYTE, REG_V12, REG_P1, REG_V15,
INS_OPTS_SCALABLE_H_TO_SIMD_SCALAR); /* CLASTA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR); /* CLASTA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_4BYTE, REG_V13, REG_P2, REG_V16,
INS_OPTS_SCALABLE_S_TO_SIMD_SCALAR); /* CLASTB <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR); /* CLASTB <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_V14, REG_P0, REG_V17,
INS_OPTS_SCALABLE_D_TO_SIMD_SCALAR); /* CLASTB <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR); /* CLASTB <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */

// IF_SVE_CO_3A
// Note: EA_4BYTE used for B and H (destination register is W)
theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_4BYTE, REG_R0, REG_P0, REG_V0,
INS_OPTS_SCALABLE_B_TO_SCALAR); /* CLASTA <R><dn>, <Pg>, <R><dn>, <Zm>.<T> */
INS_OPTS_SCALABLE_B_WITH_SCALAR); /* CLASTA <R><dn>, <Pg>, <R><dn>, <Zm>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_clasta, EA_4BYTE, REG_R1, REG_P2, REG_V3,
INS_OPTS_SCALABLE_H_TO_SCALAR); /* CLASTA <R><dn>, <Pg>, <R><dn>, <Zm>.<T> */
INS_OPTS_SCALABLE_H_WITH_SCALAR); /* CLASTA <R><dn>, <Pg>, <R><dn>, <Zm>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_4BYTE, REG_R23, REG_P5, REG_V12,
INS_OPTS_SCALABLE_S_TO_SCALAR); /* CLASTB <R><dn>, <Pg>, <R><dn>, <Zm>.<T> */
INS_OPTS_SCALABLE_S_WITH_SCALAR); /* CLASTB <R><dn>, <Pg>, <R><dn>, <Zm>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_clastb, EA_8BYTE, REG_R3, REG_P6, REG_V9,
INS_OPTS_SCALABLE_D_TO_SCALAR); /* CLASTB <R><dn>, <Pg>, <R><dn>, <Zm>.<T> */
INS_OPTS_SCALABLE_D_WITH_SCALAR); /* CLASTB <R><dn>, <Pg>, <R><dn>, <Zm>.<T> */

// IF_SVE_EP_3A
theEmitter->emitIns_R_R_R(INS_sve_shadd, EA_SCALABLE, REG_V15, REG_P0, REG_V10,
Expand Down Expand Up @@ -10300,11 +10300,11 @@ void CodeGen::genArm64EmitterUnitTests()

// IF_SVE_HJ_3A
theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_2BYTE, REG_V21, REG_P6, REG_V14,
INS_OPTS_SCALABLE_H_TO_SIMD_SCALAR); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_4BYTE, REG_V22, REG_P5, REG_V13,
INS_OPTS_SCALABLE_S_TO_SIMD_SCALAR); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_fadda, EA_8BYTE, REG_V23, REG_P4, REG_V12,
INS_OPTS_SCALABLE_D_TO_SIMD_SCALAR); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */
INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR); /* FADDA <V><dn>, <Pg>, <V><dn>, <Zm>.<T> */

// IF_SVE_HL_3A
theEmitter->emitIns_R_R_R(INS_sve_fabd, EA_SCALABLE, REG_V24, REG_P3, REG_V11,
Expand Down Expand Up @@ -10342,59 +10342,59 @@ void CodeGen::genArm64EmitterUnitTests()

// IF_SVE_AF_3A
theEmitter->emitIns_R_R_R(INS_sve_andv, EA_1BYTE, REG_V0, REG_P0, REG_V0,
INS_OPTS_SCALABLE_B_TO_SIMD_SCALAR); /* ANDV <V><d>, <Pg>, <Zn>.<T> */
INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR); /* ANDV <V><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_eorv, EA_2BYTE, REG_V1, REG_P1, REG_V1,
INS_OPTS_SCALABLE_H_TO_SIMD_SCALAR); /* EORV <V><d>, <Pg>, <Zn>.<T> */
INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR); /* EORV <V><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_orv, EA_4BYTE, REG_V2, REG_P2, REG_V2,
INS_OPTS_SCALABLE_S_TO_SIMD_SCALAR); /* ORV <V><d>, <Pg>, <Zn>.<T> */
INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR); /* ORV <V><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_orv, EA_8BYTE, REG_V3, REG_P3, REG_V3,
INS_OPTS_SCALABLE_D_TO_SIMD_SCALAR); /* ORV <V><d>, <Pg>, <Zn>.<T> */
INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR); /* ORV <V><d>, <Pg>, <Zn>.<T> */

// IF_SVE_AG_3A
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
theEmitter->emitIns_R_R_R(INS_sve_andqv, EA_1BYTE, REG_V4, REG_P4, REG_V4, INS_OPTS_SCALABLE_B_TO_SIMD_VECTOR);
theEmitter->emitIns_R_R_R(INS_sve_andqv, EA_8BYTE, REG_V4, REG_P4, REG_V4, INS_OPTS_SCALABLE_B_WITH_SIMD_VECTOR);
/* ANDQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
theEmitter->emitIns_R_R_R(INS_sve_eorqv, EA_2BYTE, REG_V5, REG_P5, REG_V5, INS_OPTS_SCALABLE_H_TO_SIMD_VECTOR);
theEmitter->emitIns_R_R_R(INS_sve_eorqv, EA_8BYTE, REG_V5, REG_P5, REG_V5, INS_OPTS_SCALABLE_H_WITH_SIMD_VECTOR);
/* EORQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_4BYTE, REG_V6, REG_P6, REG_V6, INS_OPTS_SCALABLE_S_TO_SIMD_VECTOR);
theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_8BYTE, REG_V6, REG_P6, REG_V6, INS_OPTS_SCALABLE_S_WITH_SIMD_VECTOR);
/* ORQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_8BYTE, REG_V7, REG_P7, REG_V7, INS_OPTS_SCALABLE_D_TO_SIMD_VECTOR);
theEmitter->emitIns_R_R_R(INS_sve_orqv, EA_8BYTE, REG_V7, REG_P7, REG_V7, INS_OPTS_SCALABLE_D_WITH_SIMD_VECTOR);
/* ORQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED

// IF_SVE_AI_3A
theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_1BYTE, REG_V1, REG_P4, REG_V2,
INS_OPTS_SCALABLE_B_TO_SIMD_SCALAR); /* SADDV <Dd>, <Pg>, <Zn>.<T> */
INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR); /* SADDV <Dd>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_saddv, EA_2BYTE, REG_V2, REG_P5, REG_V3,
INS_OPTS_SCALABLE_H_TO_SIMD_SCALAR); /* SADDV <Dd>, <Pg>, <Zn>.<T> */
INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR); /* SADDV <Dd>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_uaddv, EA_4BYTE, REG_V3, REG_P6, REG_V4,
INS_OPTS_SCALABLE_S_TO_SIMD_SCALAR); /* UADDV <Dd>, <Pg>, <Zn>.<T> */
INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR); /* UADDV <Dd>, <Pg>, <Zn>.<T> */

// IF_SVE_AJ_3A
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
theEmitter->emitIns_R_R_R(INS_sve_addqv, EA_8BYTE, REG_V21, REG_V7, REG_P22, INS_OPTS_SCALABLE_B_TO_SIMD_VECTOR);
theEmitter->emitIns_R_R_R(INS_sve_addqv, EA_8BYTE, REG_V21, REG_V7, REG_P22, INS_OPTS_SCALABLE_B_WITH_SIMD_VECTOR);
/* ADDQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED

// IF_SVE_AK_3A
theEmitter->emitIns_R_R_R(INS_sve_smaxv, EA_8BYTE, REG_V15, REG_P7, REG_V4,
INS_OPTS_SCALABLE_D_TO_SIMD_SCALAR); /* SMAXV <V><d>, <Pg>, <Zn>.<T> */
INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR); /* SMAXV <V><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_sminv, EA_4BYTE, REG_V16, REG_P6, REG_V14,
INS_OPTS_SCALABLE_S_TO_SIMD_SCALAR); /* SMINV <V><d>, <Pg>, <Zn>.<T> */
INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR); /* SMINV <V><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_umaxv, EA_2BYTE, REG_V17, REG_P5, REG_V24,
INS_OPTS_SCALABLE_H_TO_SIMD_SCALAR); /* UMAXV <V><d>, <Pg>, <Zn>.<T> */
INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR); /* UMAXV <V><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_uminv, EA_1BYTE, REG_V18, REG_P4, REG_V31,
INS_OPTS_SCALABLE_B_TO_SIMD_SCALAR); /* UMINV <V><d>, <Pg>, <Zn>.<T> */
INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR); /* UMINV <V><d>, <Pg>, <Zn>.<T> */

// IF_SVE_AL_3A
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
theEmitter->emitIns_R_R_R(INS_sve_smaxqv, EA_1BYTE, REG_V0, REG_P5, REG_V25, INS_OPTS_SCALABLE_B_TO_SIMD_VECTOR);
theEmitter->emitIns_R_R_R(INS_sve_smaxqv, EA_8BYTE, REG_V0, REG_P5, REG_V25, INS_OPTS_SCALABLE_B_WITH_SIMD_VECTOR);
/* SMAXQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
theEmitter->emitIns_R_R_R(INS_sve_sminqv, EA_2BYTE, REG_V1, REG_P4, REG_V24, INS_OPTS_SCALABLE_H_TO_SIMD_VECTOR);
theEmitter->emitIns_R_R_R(INS_sve_sminqv, EA_8BYTE, REG_V1, REG_P4, REG_V24, INS_OPTS_SCALABLE_H_WITH_SIMD_VECTOR);
/* SMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
theEmitter->emitIns_R_R_R(INS_sve_umaxqv, EA_4BYTE, REG_V2, REG_P3, REG_V23, INS_OPTS_SCALABLE_S_TO_SIMD_VECTOR);
theEmitter->emitIns_R_R_R(INS_sve_umaxqv, EA_8BYTE, REG_V2, REG_P3, REG_V23, INS_OPTS_SCALABLE_S_WITH_SIMD_VECTOR);
/* UMAXQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
theEmitter->emitIns_R_R_R(INS_sve_uminqv, EA_8BYTE, REG_V3, REG_P2, REG_V22, INS_OPTS_SCALABLE_D_TO_SIMD_VECTOR);
theEmitter->emitIns_R_R_R(INS_sve_uminqv, EA_8BYTE, REG_V3, REG_P2, REG_V22, INS_OPTS_SCALABLE_D_WITH_SIMD_VECTOR);
/* UMINQV <Vd>.<T>, <Pg>, <Zn>.<Tb> */
#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED

Expand Down Expand Up @@ -10444,6 +10444,76 @@ void CodeGen::genArm64EmitterUnitTests()
theEmitter->emitIns_R_R_R(INS_sve_uxtw, EA_SCALABLE, REG_V17, REG_P6, REG_V14,
INS_OPTS_SCALABLE_D); /* UXTW <Zd>.D, <Pg>/M, <Zn>.D */

// IF_SVE_CL_3A
theEmitter->emitIns_R_R_R(INS_sve_compact, EA_SCALABLE, REG_V16, REG_P7, REG_V13,
INS_OPTS_SCALABLE_S); /* COMPACT <Zd>.<T>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_compact, EA_SCALABLE, REG_V15, REG_P0, REG_V12,
INS_OPTS_SCALABLE_D); /* COMPACT <Zd>.<T>, <Pg>, <Zn>.<T> */

// IF_SVE_CP_3A
theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_1BYTE, REG_V14, REG_P1, REG_V11,
INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR); /* CPY <Zd>.<T>, <Pg>/M, <V><n> */
theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_4BYTE, REG_V13, REG_P2, REG_V10,
INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR); /* CPY <Zd>.<T>, <Pg>/M, <V><n> */
theEmitter->emitIns_R_R_R(INS_sve_mov, EA_2BYTE, REG_V12, REG_P3, REG_V9,
INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR); /* MOV <Zd>.<T>, <Pg>/M, <V><n> */
theEmitter->emitIns_R_R_R(INS_sve_mov, EA_8BYTE, REG_V11, REG_P4, REG_V8,
INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR); /* MOV <Zd>.<T>, <Pg>/M, <V><n> */

// IF_SVE_CQ_3A
// Note: EA_4BYTE used for B and H (source register is W)
theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_8BYTE, REG_V10, REG_P5, REG_SP,
INS_OPTS_SCALABLE_D_WITH_SCALAR); /* CPY <Zd>.<T>, <Pg>/M, <R><n|SP> */
theEmitter->emitIns_R_R_R(INS_sve_cpy, EA_4BYTE, REG_V9, REG_P6, REG_R30,
INS_OPTS_SCALABLE_H_WITH_SCALAR); /* CPY <Zd>.<T>, <Pg>/M, <R><n|SP> */
theEmitter->emitIns_R_R_R(INS_sve_mov, EA_4BYTE, REG_V8, REG_P7, REG_R29,
INS_OPTS_SCALABLE_S_WITH_SCALAR); /* MOV <Zd>.<T>, <Pg>/M, <R><n|SP> */
theEmitter->emitIns_R_R_R(INS_sve_mov, EA_4BYTE, REG_V7, REG_P0, REG_R28,
INS_OPTS_SCALABLE_B_WITH_SCALAR); /* MOV <Zd>.<T>, <Pg>/M, <R><n|SP> */

// IF_SVE_CR_3A
theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_1BYTE, REG_V6, REG_P1, REG_V27,
INS_OPTS_SCALABLE_B_WITH_SIMD_SCALAR); /* LASTA <V><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_2BYTE, REG_V5, REG_P2, REG_V26,
INS_OPTS_SCALABLE_H_WITH_SIMD_SCALAR); /* LASTA <V><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_4BYTE, REG_V4, REG_P3, REG_V25,
INS_OPTS_SCALABLE_S_WITH_SIMD_SCALAR); /* LASTB <V><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_8BYTE, REG_V3, REG_P4, REG_V24,
INS_OPTS_SCALABLE_D_WITH_SIMD_SCALAR); /* LASTB <V><d>, <Pg>, <Zn>.<T> */

// IF_SVE_CS_3A
// Note: EA_4BYTE used for B and H (source register is W)
theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_4BYTE, REG_R1, REG_P5, REG_V23,
INS_OPTS_SCALABLE_B_WITH_SCALAR); /* LASTA <R><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_lasta, EA_4BYTE, REG_R0, REG_P6, REG_V22,
INS_OPTS_SCALABLE_S_WITH_SCALAR); /* LASTA <R><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_4BYTE, REG_R30, REG_P7, REG_V21,
INS_OPTS_SCALABLE_H_WITH_SCALAR); /* LASTB <R><d>, <Pg>, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_lastb, EA_8BYTE, REG_R29, REG_P0, REG_V20,
INS_OPTS_SCALABLE_D_WITH_SCALAR); /* LASTB <R><d>, <Pg>, <Zn>.<T> */

// IF_SVE_CU_3A
theEmitter->emitIns_R_R_R(INS_sve_rbit, EA_SCALABLE, REG_V28, REG_P1, REG_V19,
INS_OPTS_SCALABLE_H); /* RBIT <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_rbit, EA_SCALABLE, REG_V28, REG_P1, REG_V19,
INS_OPTS_SCALABLE_B); /* RBIT <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_rbit, EA_SCALABLE, REG_V28, REG_P1, REG_V19,
INS_OPTS_SCALABLE_S); /* RBIT <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_rbit, EA_SCALABLE, REG_V28, REG_P1, REG_V19,
INS_OPTS_SCALABLE_D); /* RBIT <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_revb, EA_SCALABLE, REG_V27, REG_P2, REG_V18,
INS_OPTS_SCALABLE_H); /* REVB <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_revb, EA_SCALABLE, REG_V27, REG_P2, REG_V18,
INS_OPTS_SCALABLE_S); /* REVB <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_revb, EA_SCALABLE, REG_V27, REG_P2, REG_V18,
INS_OPTS_SCALABLE_D); /* REVB <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_revh, EA_SCALABLE, REG_V26, REG_P3, REG_V17,
INS_OPTS_SCALABLE_S); /* REVH <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_revh, EA_SCALABLE, REG_V26, REG_P3, REG_V17,
INS_OPTS_SCALABLE_D); /* REVH <Zd>.<T>, <Pg>/M, <Zn>.<T> */
theEmitter->emitIns_R_R_R(INS_sve_revw, EA_SCALABLE, REG_V25, REG_P4, REG_V16,
INS_OPTS_SCALABLE_D); /* REVW <Zd>.D, <Pg>/M, <Zn>.D */

#endif // ALL_ARM64_EMITTER_UNIT_TESTS_SVE

#ifdef ALL_ARM64_EMITTER_UNIT_TESTS
Expand Down
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