Merge branch 'reduced_poly_fill' of github.com:efabless/caravel into …

…reduced_poly_fill
efabless · Sep 4, 2024 · b7b9c26 · b7b9c26
2 parents 9d7492c + 68fefe7
commit b7b9c26
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Showing 4 changed files with 8 additions and 8 deletions.
diff --git a/verilog/gl/caravan_core.v b/verilog/gl/caravan_core.v
@@ -1336524,15 +1336524,15 @@ module caravan_core (clock_core,
  sky130_fd_sc_hd__tapvpwrvgnd_1 TAP_ECO_1 (.VGND(vssd),
     .VPWR(vccd));
 
- sky130_ef_sc_hd__decap_12 EF_decap_12[53703:0] (VGND(vssd),
+ sky130_ef_sc_hd__decap_12 EF_decap_12[53703:0] (.VGND(vssd),
     .VNB(vssd),
     .VPB(vccd),
     .VPWR(vccd));
- sky130_ef_sc_hd__fill_4 EF_fill_4[53702:0] (VGND(vssd),
+ sky130_ef_sc_hd__fill_4 EF_fill_4[53702:0] (.VGND(vssd),
     .VNB(vssd),
     .VPB(vccd),
     .VPWR(vccd)); 
- sky130_ef_sc_hd__fill_8 EF_fill_8[53702:0] (VGND(vssd),
+ sky130_ef_sc_hd__fill_8 EF_fill_8[53702:0] (.VGND(vssd),
     .VNB(vssd),
     .VPB(vccd),
     .VPWR(vccd)); 

diff --git a/verilog/gl/caravel_core.v b/verilog/gl/caravel_core.v
@@ -1298269,15 +1298269,15 @@ module caravel_core (clock_core,
     .VNB(vssd),
     .VPB(vccd),
     .VPWR(vccd));
- sky130_ef_sc_hd__decap_12 EF_decap_12[65364:0] (VGND(vssd),
+ sky130_ef_sc_hd__decap_12 EF_decap_12[65364:0] (.VGND(vssd),
     .VNB(vssd),
     .VPB(vccd),
     .VPWR(vccd));
- sky130_ef_sc_hd__fill_4 EF_fill_4[57192:0] (VGND(vssd),
+ sky130_ef_sc_hd__fill_4 EF_fill_4[57192:0] (.VGND(vssd),
     .VNB(vssd),
     .VPB(vccd),
     .VPWR(vccd)); 
- sky130_ef_sc_hd__fill_8 EF_fill_8[57192:0] (VGND(vssd),
+ sky130_ef_sc_hd__fill_8 EF_fill_8[57192:0] (.VGND(vssd),
     .VNB(vssd),
     .VPB(vccd),
     .VPWR(vccd)); 

diff --git a/verilog/gl/housekeeping.v b/verilog/gl/housekeeping.v
@@ -155461,7 +155461,7 @@ module housekeeping (VGND,
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
-  sky130_ef_sc_hd__fill_8 fill4[604:0] (.VGND(VGND),
+  sky130_ef_sc_hd__fill_8 fill8[604:0] (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));

diff --git a/verilog/gl/housekeeping_alt.v b/verilog/gl/housekeeping_alt.v
@@ -142365,7 +142365,7 @@ module housekeeping_alt (VGND,
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));
-  sky130_ef_sc_hd__fill_8 fill4[768:0] (.VGND(VGND),
+  sky130_ef_sc_hd__fill_8 fill8[768:0] (.VGND(VGND),
     .VNB(VGND),
     .VPB(VPWR),
     .VPWR(VPWR));