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caravan_core
chip_io_alt
caravan_signal_routing
caravan_power_routing
verilog/rtl/caravan_core.v
verilog/rtl/caravan.v
user_analog_project_wrapper
user_project_wrapper
housekeeping_alt
ANTGATERATIO
scripts/insert_ant_areas.py
OPENLANE_TAG
openlane/Makefile
/// sta-blackbox
ANTGATEAREA
lef/user_analog_project_wrapper_empty.lef
lef/user_project_wrapper_empty.lef
empty_macro_1
lef/chip_io_alt.lef
caravan
gds/caravan.gds.gz
max_tran=0
user_id_programming
caravan.gds.gz
export OPENLANE_TAG
vssd
vccd
e25997c