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Caravan top lvs #67

Merged
merged 8 commits into from
Apr 14, 2022
Merged

Caravan top lvs #67

merged 8 commits into from
Apr 14, 2022

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RTimothyEdwards
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See commit notes. Merging probably fails on the mgmt_protect layout and subcells. Please cherry-pick the rest of the files for merging.

kareefardi and others added 7 commits April 13, 2022 14:48
* change correct gpio_default blocks instance names
* implement powerrouting work around
* place spare logic blocks
* keep the history of runs and sym link last/final one
- add fake power routing cell in the rtl as a placeholder for openlane
  to prevent routing on that cell
- fix some syntax errors in chip_io_alt
- match simple_por lef pins with mag by regenerating it
- add_macro_placement for fake cell
corrected placement of isolated substrate regions, and replaced the
signal routing for the analog lines.  Be aware that merging with
main may cause issues with the mgmt_protect.mag file and its
subcells mprj2_logic_high.mag and mprj_logic_high.mag.  It may be
worth cherry-picking the files to merge and exclude those layouts.
@RTimothyEdwards
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Or maybe it doesn't have issues with those files. It only seems to be complaining about openlane/Makefile.

@jeffdi jeffdi self-requested a review April 14, 2022 21:56
@jeffdi jeffdi merged commit 7160044 into main Apr 14, 2022
@jeffdi jeffdi deleted the caravan_top_lvs branch April 14, 2022 22:05
antonblanchard pushed a commit to antonblanchard/caravel that referenced this pull request Apr 27, 2022
M0stafaRady pushed a commit that referenced this pull request Sep 30, 2022
* - update caravan configuration
* change correct gpio_default blocks instance names
* implement powerrouting work around
* place spare logic blocks
* keep the history of runs and sym link last/final one

* - update caravan mag, def and gl views
- add fake power routing cell in the rtl as a placeholder for openlane
  to prevent routing on that cell
- fix some syntax errors in chip_io_alt
- match simple_por lef pins with mag by regenerating it

* Apply automatic changes to Manifest and README.rst

* add caravan power routing lef

* - update mag and def view of caravan
- add_macro_placement for fake cell

* Added back the power routing to Caravan, fixed DRC errors, ran LVS,
corrected placement of isolated substrate regions, and replaced the
signal routing for the analog lines.  Be aware that merging with
main may cause issues with the mgmt_protect.mag file and its
subcells mprj2_logic_high.mag and mprj_logic_high.mag.  It may be
worth cherry-picking the files to merge and exclude those layouts.

Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
@RTimothyEdwards RTimothyEdwards added error Something isn't working RTL Verilog source code changed PnR Gate level verilog and/or layout changed labels Oct 4, 2022
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3 participants