[wip] add cocotb tests

verilog/dv/cocotb/.gitignore

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+sim/ 
+*.log
+*.vcd 
+*.pyc

verilog/dv/cocotb/README.md

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+Overview
+======== 
+This directory contain tests to verify the example user project 16 bit counter and 2 other simple tests as examples. 
+
+directory hierarchy
+=====================
+
+# counter_tests 
+
+contain tests for 16 bit counter for more info refer to [counter_tests](counter_tests/README.md)
+
+ # hello_world 
+
+ Example test with empty firmware that only power and reset caravel the print "Hello World" 
+
+ # hello_world_uart 
+
+ Example test That uses the firmware to send "Hello World" using UART TX 
+
+ # cocotb_includes.py
+
+ Read only file that imports cocotb based APIs. needed to be imported on the test to use the cocotb based APIs. 
+
+
+# cocotb_tests.py 
+
+Module that should import all the tests used to be seen for cocotb as a test
+
+
+

verilog/dv/cocotb/all_tests/PoR/PoR.c

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+/*
+ * SPDX-FileCopyrightText: 2020 Efabless Corporation
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *      http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <firmware_apis.h>
+
+
+
+// --------------------------------------------------------
+
+/*
+ *	Management SoC GPIO Pin Test
+ *		Tests writing to the GPIO pin.
+ */
+
+void main(){
+    enable_debug();
+    enableHkSpi(0);
+    ManagmentGpio_inputEnable();
+    int num_blinks = 0;
+    set_debug_reg1(0XAA); // start of the test
+	while (1) {
+        ManagmentGpio_wait(0);
+        ManagmentGpio_wait(1);
+        num_blinks++;
+        if (get_debug_reg1() == 0xFF)
+            break;
+	}
+    ManagmentGpio_outputEnable();
+	for (int i = 0; i < num_blinks; i++) {
+		/* Fast blink for simulation */
+        ManagmentGpio_write(1);
+        dummyDelay(10);
+        ManagmentGpio_write(0);
+        dummyDelay(10);
+	}
+    set_debug_reg2(0XFF); //finish test
+    dummyDelay(10000000);
+}
+

verilog/dv/cocotb/all_tests/PoR/PoR.py

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+import random
+import cocotb
+from cocotb.triggers import ClockCycles, Timer
+import cocotb.log
+from caravel_cocotb.caravel_interfaces import report_test
+from caravel_cocotb.caravel_interfaces import Caravel_env
+from caravel_cocotb.interfaces.common_functions.test_functions import max_num_error
+from caravel_cocotb.interfaces.common_functions.test_functions import read_config_file
+from cocotb.binary import BinaryValue
+from caravel_cocotb.interfaces.common_functions.test_functions import Timeout
+from all_tests.mgmt_gpio.mgmt_gpio import blink_counter
+from user_design import configure_userdesign
+from cocotb.clock import Clock
+
+
+@cocotb.test()
+@report_test
+async def PoR(dut):
+    # configurations
+    caravelEnv = Caravel_env(dut)
+    Timeout(clk=caravelEnv.clk, cycle_num=1904502, precision=0.2)
+    cocotb.scheduler.add(max_num_error(10, caravelEnv.clk))
+    clock = Clock(
+        caravelEnv.clk, read_config_file()["clock"], units="ns"
+    )  # Create a 25ns period clock on port clk
+    cocotb.start_soon(clock.start())  # Start the clock
+    # drive reset with 1
+    await caravelEnv.disable_csb()  #
+    caravelEnv.dut.resetb_tb.value = BinaryValue(value=1, n_bits=1)
+    await caravelEnv.power_up()
+    await Timer(530, "ns")
+    # await caravelEnv.reset() #
+    await caravelEnv.disable_bins()
+    debug_regs = await configure_userdesign(caravelEnv)
+
+    # start test
+    cocotb.log.info("[TEST] Start mgmt_gpio_bidir test")
+
+    await debug_regs.wait_reg1(0xAA)
+    num_blinks = random.randint(1, 20)
+    cocotb.log.info(f"[TEST] start send {num_blinks} blinks")
+    for i in range(num_blinks):
+        if i == num_blinks - 1:  # last iteration
+            debug_regs.write_debug_reg1_backdoor(0xFF)
+        caravelEnv.drive_mgmt_gpio(1)
+        await ClockCycles(caravelEnv.clk, 30000)
+        caravelEnv.drive_mgmt_gpio(0)
+        if i != num_blinks - 1:  # not last iteration
+            await ClockCycles(caravelEnv.clk, 30000)
+        else:
+            # caravelEnv.drive_mgmt_gpio('z')
+            await ClockCycles(caravelEnv.clk, 1)
+
+    # caravelEnv.drive_mgmt_gpio('z')
+    cocotb.log.info(f"[TEST] finish sending {num_blinks} blinks ")
+
+    cocotb.log.info(f"[TEST] waiting for {num_blinks} blinks ")
+    counter = [0]  # list to pass by ref
+    # forked
+    await cocotb.start(blink_counter(caravelEnv.get_mgmt_gpi_hdl(), counter))
+    await debug_regs.wait_reg2(0xFF)
+    recieved_blinks = counter[0]
+    if recieved_blinks == num_blinks:
+        cocotb.log.info(f"[TEST] recieved the correct number of blinks {num_blinks}")
+    else:
+        cocotb.log.error(
+            f"[TEST] recieved the incorrect number of blinks recieved = {recieved_blinks} expected = {num_blinks}"
+        )
+    cocotb.log.info(f"[TEST] counter =  {counter}")
+
+    if recieved_blinks == num_blinks:
+        cocotb.log.info(f"[TEST] recieved the correct number of blinks {num_blinks}")
+    else:
+        cocotb.log.error(
+            f"[TEST] recieved the incorrect number of blinks recieved = {recieved_blinks} expected = {num_blinks}"
+        )

verilog/dv/cocotb/all_tests/bitbang/bitbang_cpu_all_i.c

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+#include <firmware_apis.h>
+
+#include <bitbang.h>
+
+void main(){
+    enable_debug();
+    enableHkSpi(0);
+    bb_configureAllGpios(GPIO_MODE_MGMT_STD_INPUT_NOPULL);
+    // low
+    wait_over_input_l(0xAA,0xFFFFFFFF);
+    wait_over_input_l(0XBB,0xAAAAAAAA);
+    wait_over_input_l(0XCC,0x55555555);
+    wait_over_input_l(0XDD,0x0);
+    // high
+    wait_over_input_h(0XD1,0x3F);
+    wait_over_input_h(0XD2,0x0);
+    wait_over_input_h(0XD3,0x15);
+    wait_over_input_h(0XD4,0x2A);
+
+    // trying to inject error by sending data to gpio by firmware where gpios configured as input 
+    set_debug_reg1(0XD5);
+    set_debug_reg1(0XD5); // for delay insertion for release
+    GPIOs_writeLow(0x5AE1FFB8); // random number
+    GPIOs_writeHigh(0x1E); // random number
+    set_debug_reg2(0xFF);
+}
+
+void wait_over_input_l(unsigned int start_code, unsigned int exp_val){
+    set_debug_reg1(start_code); // configuration done wait environment to send exp_val to reg_mprj_datal
+    GPIOs_waitLow(exp_val);
+    set_debug_reg2(GPIOs_readLow());
+
+}
+void wait_over_input_h(unsigned int start_code, unsigned int exp_val){
+    set_debug_reg1(start_code); 
+    GPIOs_waitHigh(exp_val);
+    set_debug_reg2(GPIOs_readHigh());
+}

verilog/dv/cocotb/all_tests/bitbang/bitbang_cpu_all_o.c

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+#include <firmware_apis.h>
+
+#include <bitbang.h>
+void main(){
+        unsigned int i,i_temp, j, active_gpio_num,num_high_gpio;
+        enable_debug();
+        enableHkSpi(0);
+        bb_configureAllGpios(GPIO_MODE_MGMT_STD_OUTPUT);        
+        set_debug_reg1(0xAA); // finish configuration 
+        GPIOs_writeLow(0x0);
+        GPIOs_writeHigh(0x0);
+        active_gpio_num = get_active_gpios_num();
+        num_high_gpio = (active_gpio_num - 32);
+        i = 0x1 << num_high_gpio;
+        i_temp = i;
+        for (j = 0; j <= num_high_gpio; j++) {
+                GPIOs_writeHigh(i);
+                set_debug_reg2(active_gpio_num+1-j);
+                wait_debug_reg1(0xD1); // wait until wait until test read 1
+                GPIOs_writeHigh(0x0);
+                set_debug_reg2(0);
+                wait_debug_reg1(0xD0);// wait until test read 0
+                i >>=1;
+                i |= i_temp;
+        }
+        i = 0x80000000;
+        for (j = 0; j < 32; j++) {
+                GPIOs_writeHigh(0x3f);
+                GPIOs_writeLow(i);
+                set_debug_reg2(32-j);
+                wait_debug_reg1(0xD1); // wait until test read 1
+                GPIOs_writeHigh(0x00);
+                GPIOs_writeLow(0x0);
+                set_debug_reg2(0);
+                wait_debug_reg1(0xD0);// wait until test read 0
+                i >>=1;
+                i |= 0x80000000;
+        }
+        set_debug_reg1(0XFF); // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal
+}

verilog/dv/cocotb/all_tests/bitbang/bitbang_no_cpu.c

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+#include <defs.h>
+#include <stub.c>
+
+// Empty C code
+
+void main()
+{
+	return;
+}
+

verilog/dv/cocotb/all_tests/bitbang/bitbang_no_cpu_all_i.c

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+#include <defs.h>
+#include <stub.c>
+
+// Empty C code
+
+void main()
+{
+	return;
+}
+

verilog/dv/cocotb/all_tests/bitbang/bitbang_no_cpu_all_o.c

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+#include <defs.h>
+#include <stub.c>
+
+// Empty C code
+
+void main()
+{
+	return;
+}