fixed config file

Makefile

@@ -85,7 +85,7 @@ ifeq ($(PDK),gf180mcuD)
 	CARAVEL_TAG := $(MPW_TAG)
 	#OPENLANE_TAG=ddfeab57e3e8769ea3d40dda12be0460e09bb6d9
 	export OPEN_PDKS_COMMIT?=dd7771c384ed36b91a25e9f8b314355fc26561be
-	export OPENLANE_TAG?=2023.07.19
+	export OPENLANE_TAG?=2023.10.10
 
 endif
 

openlane/user_proj_example/config.json

@@ -11,19 +11,20 @@
 	"CLOCK_NET": "counter.clk",
 	"CLOCK_PERIOD": "24.0",
 	"FP_SIZING": "absolute",
-	"DIE_AREA": "0 0 900 600",
-	"FP_PIN_ORDER_CFG": "pin_order.cfg",
+	"DIE_AREA": "0 0 2800 1760",
+	"FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
 	"PL_BASIC_PLACEMENT": 0,
 	"PL_TARGET_DENSITY": 0.45,
 	"FP_CORE_UTIL": 40,
 	"SYNTH_MAX_FANOUT": 4,
-	"RT_MAX_LAYER": "met4",
+	"RT_MAX_LAYER": "Metal4",
 	"VDD_NETS": [
-		"vccd1"
+		"vdd"
 	],
 	"GND_NETS": [
-		"vssd1"
+		"vss"
 	],
 	"DIODE_INSERTION_STRATEGY": 4,
-	"RUN_CVC": 1
+	"RUN_CVC": 1,
+	"QUIT_ON_LINTER_ERRORS": 0
 }

openlane/user_proj_example/pin_order.cfg

@@ -6,5 +6,54 @@ wbs_.*
 la_.*
 irq.*
 
-#N
-io_.*
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+
+#WR
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]

openlane/user_project_wrapper/config.json

@@ -1,5 +1,6 @@
 {
 	"PDK": "gf180mcuD",
+	"DESIGN_NAME": "user_project_wrapper",
 	"STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
 	"VERILOG_FILES": [
 		"dir::../../verilog/rtl/defines.v",
@@ -8,29 +9,43 @@
 	"CLOCK_PORT": "user_clock2",
 	"CLOCK_NET": "mprj.clk",
 	"CLOCK_PERIOD": "10",
-	"FP_PDN_MACRO_HOOKS": "mprj vccd1 vssd1 vccd1 vssd1",
-	"MACRO_PLACEMENT_CFG": "macro.cfg",
+	"MACRO_PLACEMENT_CFG": "dir::macro.cfg",
 	"VERILOG_FILES_BLACKBOX": [
 		"dir::../../verilog/gl/user_proj_example.v"
 	],
+	"EXTRA_LEFS": "dir::../../lef/user_proj_example.lef",
+	"EXTRA_GDS_FILES": "dir::../../gds/user_proj_example.gds",
+	"EXTRA_LIBS": "dir::../../lib/user_proj_example.lib",
+	"EXTRA_SPEFS": [
+		"user_proj_example",
+		"dir::../../spef/multicorner/user_proj_example.min.spef",
+		"dir::../../spef/multicorner/user_proj_example.nom.spef",
+		"dir::../../spef/multicorner/user_proj_example.max.spef"
+	],
+	"FP_PDN_MACRO_HOOKS": "mprj vdd vss vdd vss",
+	"QUIT_ON_SYNTH_CHECKS": 0,
 	"FP_PDN_CHECK_NODES": 0,
 	"SYNTH_ELABORATE_ONLY": 1,
 	"PL_RANDOM_GLB_PLACEMENT": 1,
 	"PL_RESIZER_DESIGN_OPTIMIZATIONS": 0,
 	"PL_RESIZER_TIMING_OPTIMIZATIONS": 0,
+	"GLB_RESIZER_DESIGN_OPTIMIZATIONS": 0,
+	"GLB_RESIZER_TIMING_OPTIMIZATIONS": 0,
 	"PL_RESIZER_BUFFER_INPUT_PORTS": 0,
-	"PL_RESIZER_BUFFER_OUTPUT_PORTS": 0,
 	"FP_PDN_ENABLE_RAILS": 0,
+	"GRT_REPAIR_ANTENNAS": 0,
 	"DIODE_INSERTION_STRATEGY": 0,
+	"DIODE_ON_PORTS": "None",
+	"RUN_HEURISTIC_DIODE_INSERTION": 0,
 	"RUN_FILL_INSERTION": 0,
 	"RUN_TAP_DECAP_INSERTION": 0,
-	"CLOCK_TREE_SYNTH": 0,
+	"RUN_CTS": 0,
 	"MAGIC_ZEROIZE_ORIGIN": 0,
 	"FP_SIZING": "absolute",
 	"DIE_AREA": "0 0 2980.2 2980.2",
 	"CORE_AREA": "12 12 2968.2 2968.2",
 	"RUN_CVC": 0,
-	"FP_PIN_ORDER_CFG": "pin_order.cfg",
+	"FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
 	"UNIT": 2.4,
 	"FP_IO_VEXTEND": "expr::2 * $UNIT",
 	"FP_IO_HEXTEND": "expr::2 * $UNIT",
@@ -59,5 +74,5 @@
 		"vss"
 	],
 	"SYNTH_USE_PG_PINS_DEFINES": "USE_POWER_PINS",
-	"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def"
+	"RUN_LINTER": 0
 }

openlane/user_project_wrapper/macro.cfg

@@ -1 +1 @@
-mprj 1175 1690 N
+mprj 60 15 N

verilog/rtl/user_proj_example.v

@@ -36,7 +36,7 @@
  */
 
 module user_proj_example #(
-    parameter BITS = 32
+    parameter BITS = 16
 )(
 `ifdef USE_POWER_PINS
     inout vdd,	// User area 1 1.8V supply
@@ -61,48 +61,44 @@ module user_proj_example #(
     input  [63:0] la_oenb,
 
     // IOs
-    input  [`MPRJ_IO_PADS-1:0] io_in,
-    output [`MPRJ_IO_PADS-1:0] io_out,
-    output [`MPRJ_IO_PADS-1:0] io_oeb,
+    input  [BITS-1:0] io_in,
+    output [BITS-1:0] io_out,
+    output [BITS-1:0] io_oeb,
 
     // IRQ
     output [2:0] irq
 );
     wire clk;
     wire rst;
 
-    wire [`MPRJ_IO_PADS-1:0] io_in;
-    wire [`MPRJ_IO_PADS-1:0] io_out;
-    wire [`MPRJ_IO_PADS-1:0] io_oeb;
-
-    wire [31:0] rdata; 
-    wire [31:0] wdata;
+    wire [BITS-1:0] rdata; 
+    wire [BITS-1:0] wdata;
     wire [BITS-1:0] count;
 
     wire valid;
     wire [3:0] wstrb;
-    wire [31:0] la_write;
+    wire [BITS-1:0] la_write;
 
     // WB MI A
     assign valid = wbs_cyc_i && wbs_stb_i; 
     assign wstrb = wbs_sel_i & {4{wbs_we_i}};
-    assign wbs_dat_o = rdata;
-    assign wdata = wbs_dat_i;
+    assign wbs_dat_o = {{(32-BITS){1'b0}}, rdata};
+    assign wdata = wbs_dat_i[BITS-1:0];
 
     // IO
     assign io_out = count;
-    assign io_oeb = {(`MPRJ_IO_PADS-1){rst}};
+    assign io_oeb = {(BITS){rst}};
 
     // IRQ
     assign irq = 3'b000;	// Unused
 
     // LA
-    assign la_data_out = {{(127-BITS){1'b0}}, count};
-    // Assuming LA probes [63:32] are for controlling the count register  
-    assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
-    // Assuming LA probes [65:64] are for controlling the count clk & reset  
-    assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
-    assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
+    assign la_data_out = {{(64-BITS){1'b0}}, count};
+    // Assuming LA probes [32:16] are for controlling the count register  
+    assign la_write = ~la_oenb[32:16] & ~{BITS{valid}};
+    // Assuming LA probes [34:33] are for controlling the count clk & reset  
+    assign clk = (~la_oenb[33]) ? la_data_in[33]: wb_clk_i;
+    assign rst = (~la_oenb[34]) ? la_data_in[34]: wb_rst_i;
 
     counter #(
         .BITS(BITS)
@@ -112,17 +108,17 @@ module user_proj_example #(
         .ready(wbs_ack_o),
         .valid(valid),
         .rdata(rdata),
-        .wdata(wbs_dat_i),
+        .wdata(wbs_dat_i[BITS-1:0]),
         .wstrb(wstrb),
         .la_write(la_write),
-        .la_input(la_data_in[63:32]),
+        .la_input(la_data_in[31:32-BITS]),
         .count(count)
     );
 
 endmodule
 
 module counter #(
-    parameter BITS = 32
+    parameter BITS = 16
 )(
     input clk,
     input reset,
@@ -131,13 +127,10 @@ module counter #(
     input [BITS-1:0] wdata,
     input [BITS-1:0] la_write,
     input [BITS-1:0] la_input,
-    output ready,
-    output [BITS-1:0] rdata,
-    output [BITS-1:0] count
+    output reg ready,
+    output reg [BITS-1:0] rdata,
+    output reg [BITS-1:0] count
 );
-    reg ready;
-    reg [BITS-1:0] count;
-    reg [BITS-1:0] rdata;
 
     always @(posedge clk) begin
         if (reset) begin
@@ -153,8 +146,6 @@ module counter #(
                 rdata <= count;
                 if (wstrb[0]) count[7:0]   <= wdata[7:0];
                 if (wstrb[1]) count[15:8]  <= wdata[15:8];
-                if (wstrb[2]) count[23:16] <= wdata[23:16];
-                if (wstrb[3]) count[31:24] <= wdata[31:24];
             end else if (|la_write) begin
                 count <= la_write & la_input;
             end

verilog/rtl/user_project_wrapper.v

@@ -31,7 +31,7 @@
 
 module user_project_wrapper #(
     parameter BITS = 32
-)(
+) (
 `ifdef USE_POWER_PINS
     inout vdd,		// User area 5.0V supply
     inout vss,		// User area ground
@@ -98,9 +98,9 @@ user_proj_example mprj (
 
     // IO Pads
 
-    .io_in (io_in),
-    .io_out(io_out),
-    .io_oeb(io_oeb),
+    .io_in ({io_in[37:30],io_in[7:0]}),
+    .io_out({io_out[37:30],io_out[7:0]}),
+    .io_oeb({io_oeb[37:30],io_oeb[7:0]}),
 
     // IRQ
     .irq(user_irq)