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fix counter_wb and counter_la_reset tests for iverilog
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M0stafaRady committed Nov 26, 2023
1 parent f16a6c6 commit 55225ac
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Showing 3 changed files with 11 additions and 4 deletions.
Original file line number Diff line number Diff line change
Expand Up @@ -31,7 +31,7 @@ void main(){
GPIOs_loadConfigs(); // load the configuration
// reset counter
#ifdef GF180
LogicAnalyzer_outputEnable(1,0x3FFFFFFF);
LogicAnalyzer_outputEnable(1,0x7FFFFFFF);
LogicAnalyzer_write(1,0x80000000);
LogicAnalyzer_write(1,0);
#else
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Original file line number Diff line number Diff line change
Expand Up @@ -44,7 +44,7 @@ async def counter_la_reset(dut):
if await get_reset_val(caravelEnv) == 0:
cocotb.log.info(f"[TEST] Reset deasserted by la")
break
counter =0
counter =int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2)

for i in range(100):
if counter != int ((caravelEnv.monitor_gpio(37,30).binstr + caravelEnv.monitor_gpio(7,0).binstr ),2) :
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11 changes: 9 additions & 2 deletions verilog/dv/cocotb/user_proj_tests/counter_wb/counter_wb.c
Original file line number Diff line number Diff line change
Expand Up @@ -25,11 +25,18 @@ void main(){

GPIOs_loadConfigs(); // load the configuration
User_enableIF(); // this necessary when reading or writing between wishbone and user project if interface isn't enabled no ack would be recieve and the command will be stuck
// user la reset and wb clk
LogicAnalyzer_outputEnable(2,1);
// user la reset and wb
// reset counter
#ifdef GF180
LogicAnalyzer_outputEnable(1, 0x7FFFFFFF);
LogicAnalyzer_write(1,0x80000000);
LogicAnalyzer_write(1,0x0);
#else
LogicAnalyzer_outputEnable(2,1);
LogicAnalyzer_write(2,2);
LogicAnalyzer_write(2,0);
#endif // GF180

ManagmentGpio_write(1); // configuration finished
// writing to any address inside user project address space would reload the counter value
USER_writeWord(0x7,0x88);
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