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Fixed to pass with verilator --lint-only. #282

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Fixed to pass with verilator --lint-only. #282

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2 changes: 1 addition & 1 deletion verilog/rtl/defines.v
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Original file line number Diff line number Diff line change
Expand Up @@ -63,4 +63,4 @@
`define OENB_INIT 1'b0
`define DM_INIT 3'b001

`endif // __GLOBAL_DEFINE_H
`endif // __GLOBAL_DEFINE_H
26 changes: 14 additions & 12 deletions verilog/rtl/user_proj_example.v
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Expand Up @@ -36,7 +36,7 @@
*/

module user_proj_example #(
parameter BITS = 16
parameter BITS = 32
)(
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
Expand All @@ -61,9 +61,9 @@ module user_proj_example #(
input [127:0] la_oenb,

// IOs
input [BITS-1:0] io_in,
output [BITS-1:0] io_out,
output [BITS-1:0] io_oeb,
input wire [15:0] io_in,
output wire [15:0] io_out,
output wire [15:0] io_oeb,

// IRQ
output [2:0] irq
Expand All @@ -82,20 +82,20 @@ module user_proj_example #(
// WB MI A
assign valid = wbs_cyc_i && wbs_stb_i;
assign wstrb = wbs_sel_i & {4{wbs_we_i}};
assign wbs_dat_o = {{(32-BITS){1'b0}}, rdata};
assign wdata = wbs_dat_i[BITS-1:0];
assign wbs_dat_o = rdata;
assign wdata = wbs_dat_i[31:0];

// IO
assign io_out = count;
assign io_oeb = {(BITS){rst}};
assign io_out = count[15:0];
assign io_oeb = {(16){rst}};

// IRQ
assign irq = 3'b000; // Unused

// LA
assign la_data_out = {{(128-BITS){1'b0}}, count};
// Assuming LA probes [63:32] are for controlling the count register
assign la_write = ~la_oenb[63:64-BITS] & ~{BITS{valid}};
assign la_write = ~la_oenb[63:32] & ~{BITS{valid}};
// Assuming LA probes [65:64] are for controlling the count clk & reset
assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
Expand All @@ -108,17 +108,17 @@ module user_proj_example #(
.ready(wbs_ack_o),
.valid(valid),
.rdata(rdata),
.wdata(wbs_dat_i[BITS-1:0]),
.wdata(wbs_dat_i),
.wstrb(wstrb),
.la_write(la_write),
.la_input(la_data_in[63:64-BITS]),
.la_input(la_data_in[63:32]),
.count(count)
);

endmodule

module counter #(
parameter BITS = 16
parameter BITS = 32
)(
input clk,
input reset,
Expand Down Expand Up @@ -146,6 +146,8 @@ module counter #(
rdata <= count;
if (wstrb[0]) count[7:0] <= wdata[7:0];
if (wstrb[1]) count[15:8] <= wdata[15:8];
if (wstrb[2]) count[23:16] <= wdata[23:16];
if (wstrb[3]) count[31:24] <= wdata[31:24];
end else if (|la_write) begin
count <= la_write & la_input;
end
Expand Down