Update Makefile to pip caravel-cocotb

[M0stafaRady]

new version of caravel-cocotb script. It should fix #303.

Please delete the branch after merge.

[marwaneltoukhy]

Can you add the installation and running inside venv?

[marwaneltoukhy]

Looks like you updated the target names, can you update it in the documentation as well? (make sure that you're updating the correct documentation). Also the name of the test from counter_tests/counter_tests.yaml to user_proj_tests/user_proj_tests.yaml, so you need to update the name of the files.

[marwaneltoukhy]

I get this error

caravel_cocotb -tl user_proj_tests/user_proj_tests.yaml
Run tag: run_21_Sep_10_38_56_85 
Start running test:  RTL-counter_la 
     -.--ns INFO     gpi                                ..mbed/gpi_embed.cpp:76   in set_program_name_in_venv        Did not detect Python virtual environment. Using system-wide Python interpreter
     -.--ns INFO     gpi                                ../gpi/GpiCommon.cpp:101  in gpi_print_registered_impl       VPI registered
/home/marwan/user_project/verilog/dv/cocotb/sim/run_21_Sep_10_38_56_85/RTL-compilation/sim.vvp: Unable to open input file.
Error: Fail to compile the verilog code for more info refer to /home/marwan/user_project/verilog/dv/cocotb/sim/run_21_Sep_10_38_56_85/RTL-compilation/compilation.log
Start running test:  RTL-counter_wb 
     -.--ns INFO     gpi                                ..mbed/gpi_embed.cpp:76   in set_program_name_in_venv        Did not detect Python virtual environment. Using system-wide Python interpreter
     -.--ns INFO     gpi                                ../gpi/GpiCommon.cpp:101  in gpi_print_registered_impl       VPI registered
/home/marwan/user_project/verilog/dv/cocotb/sim/run_21_Sep_10_38_56_85/RTL-compilation/sim.vvp: Unable to open input file.
Error: Fail to compile the verilog code for more info refer to /home/marwan/user_project/verilog/dv/cocotb/sim/run_21_Sep_10_38_56_85/RTL-compilation/compilation.log
Start running test:  RTL-counter_la_reset 
     -.--ns INFO     gpi                                ..mbed/gpi_embed.cpp:76   in set_program_name_in_venv        Did not detect Python virtual environment. Using system-wide Python interpreter
     -.--ns INFO     gpi                                ../gpi/GpiCommon.cpp:101  in gpi_print_registered_impl       VPI registered
/home/marwan/user_project/verilog/dv/cocotb/sim/run_21_Sep_10_38_56_85/RTL-compilation/sim.vvp: Unable to open input file.
Error: Fail to compile the verilog code for more info refer to /home/marwan/user_project/verilog/dv/cocotb/sim/run_21_Sep_10_38_56_85/RTL-compilation/compilation.log
Start running test:  RTL-counter_la_clk 
     -.--ns INFO     gpi                                ..mbed/gpi_embed.cpp:76   in set_program_name_in_venv        Did not detect Python virtual environment. Using system-wide Python interpreter
     -.--ns INFO     gpi                                ../gpi/GpiCommon.cpp:101  in gpi_print_registered_impl       VPI registered
/home/marwan/user_project/verilog/dv/cocotb/sim/run_21_Sep_10_38_56_85/RTL-compilation/sim.vvp: Unable to open input file.
Error: Fail to compile the verilog code for more info refer to /home/marwan/user_project/verilog/dv/cocotb/sim/run_21_Sep_10_38_56_85/RTL-compilation/compilation.log

I attached the compilation log, it has errors in the include.
compilation.log

[M0stafaRady]

I'm aware of this error.
This pull request should solve it: efabless/caravel#488