(RTL) IDE

RTL

Available tools

Meant for HDL

• Free/Open source:
  • Signs supports VHDL [BSD]
  • VisualHDL supports THDL++ [SVN LGPL]
  • Based on Eclipse
    • ngDesign supports Cx | GitHub [EPL & BSD]
    • Simplifide [EPL]
  • logisim-evolution
    • Digital
• Closed source:
  • Based on Eclipse
    • Sigasi Premium Doc supports VHDL
  • RTLvision supports VHDL, Verilog and SystemVerilog
  • HDL Designer supports VHDL, Verilog and SystemVerilog
  • Active-HDL Block Diagram Editor
  • Vivado IP Integrator
  • ISE Schematic Design
  • Simulink and System Generator
  • Labview
  • DVT Eclipse IDE
• Adacemia
  • VHDLVisualizer

Not meant for HDL

• Free/Open source:

  • draw.io supports JavaScript | GitHub:jgraph/mxgraph
  • Fritzing supports C [GitHub:fritzing GPL & CC-by-sa]
  • Dia Diagram Editor | GPL
  • Pencil supports JavaScript, XUL and SVG | GPL

• Closed source:

  • yFiles | Closed

• Diagramming software list at Wikipedia

Videogames

• Shenzhen I/O
• TIS-100

Discrete digital part circuit simulators available online:

• logic-lab supports Flash
• PartSim
• CircuitLab
• DoCircuits
• DC/AC Virtual Lab

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Desired features

• Orthogonal layout (optional).
• Visual settings configuration templates (optional): main colors, rounded edges, splines, label fonts (size, decoration, etc.)...
• Built-in parts:
  • Libraries as in HDL Designer.
  • AND, OR, NOT, XOR, NAND, NOR, XNOR
  • FF: rising, falling, (not) en, (not) rst, (not) D, (not) Q
  • Incrementer/decrementer
  • Mux
  • Constant (implicit/explicit)
  • Comparators: eq, geq, neq
  • Resize, shift left, shift right
  • Adder, multiplier... Full specification of how the arithmetic operations are performed: casting of word-lengths, truncation/rounding mode, etc. A good reference is the Fixed-Point Designer in MATLAB, or the FPHDL library.
  • Bit-level split (range) and merge (concatenate)
  • RAM/ROM
  • Glue, a virtual module to represent the complex descriptions which are not directly parsed.
• Declaration and graphication of entities/blocks even without declared architecture.
• Highlighting of the code when a signal or block is selected, if the source has been previously opened.
• Bus signal type, which groups a set of actually defined ports.
• Collapse and expande nodes, buses and modules as in VisualHDL and RTLvision.
• Make/modify connections between modules/components graphically with (optional) valid connection checking as in Vivado IP Integrator.
• Move boxes and wires graphically (multipoint paths).
• Select the location of pins as in Active-HDL Block Diagram Editor.
• Automatic arrangement as in Vivado IP Integrator.
• Create a level of hierarchy (module/component/entity) with a selected group of blocks as in Vivado IP Integrator.
• Multiple libreries for enhanced reusability.
• Adding notes and explanatory graphical elements (as a different tool subset, to aid in the documentation).
• Compact/verbose realizations (conversion from graph to HDL).
• Configurable mouse controls and shortcuts.
• Scaling of modules, selective zoom. Besides the general zoom, increase the size of the selected component.
• Export to PNG, PDF, SVG...
• Shortcut to clean unconnected wires.
• Animate simulations (smart blocks) as in logic-lab.
• Option and shortkey to disable the automatic tracking code/graph/hierarchy, to improve performance.
• Multiple windows of the graph, with different zoom and positions as in RTLvision.
• 3D view.
• Highlight a path, given a wire in it as in RTLvision.
• Configurable grid (optional).

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• Sigasi Premium Doc: Generate Block Diagrams shows in a video:
  • Diagrams get updated as you write (structural level, not the architectures).
  • If a module or wire is selected, the corresponding code is highlighted.
  • No further integration between the diagram view and the code.