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Welcome to the elide wiki!

This is a shared knowledge-base to put together references about modern and feature-rich development tools for embedded logic design. The main aim is to provide a standard open-source framework so that a user can set up a base collection of modules, and further configure them to eventually achieve a fully personalized environment.

Certainly, embedded design is a very wide target, so let us specify: we are willing to learn about embedded software and reconfigurable logic engineering, focusing on the adoption of good design practices and getting a big picture of the EDA industry. Taking low-cost and preferredly free or open source platforms as a base, the main goal is to integrate tools in order to work with embedded processors, microcontrollers and reconfigurable devices, such as CPLDs and FPGAs. Since we agree with both Nicolas Bize when he claims that "tools are only as sharp as you decide them to be" [1], and with Reiner Hartenstein on the need of a "paradigm switch" [2] [3] [4], we try to provide a framework which is modular enough so that the user can use both familiar environments/workflows and state-of-the-art solutions that better map to the target application.

The following are some of the target platforms:

• Wiring [5], Arduino [6][7], megaAVR [8],...
• PIC [9]
• Beaglebone [10], Raspberry Pi [11], CHIP [12]
• Mojo [13], LogiFPGA [14], Spartan6 [15], [16], [17],...
• Zynq [18] [19]
• icestick [20] [21], Kéfir [22], icoBOARD [23], NandlandGoBoard [24], IceZUM Alhambra [25], iCE40 [26], ...

Consequently, some of the languages in the scope are ASM, C/C++, Processing/Arduino, and VHDL/Verilog. Nevertheless, higher level languages are also considered in the framework, such as Golang, Haskell, Python, Ruby and Java.

The mainstream workflows for all of the aforementioned resources and tools are quite different, sometimes opposite. Furthermore, multiple alternatives exist for each of them. Then, the main goal is to try multiple freely available tools and summarize the most important features that we'd like the framework to cover. On top of that, if the available features/tools are free/libre [27], resources to help installing/configuring are given. Otherwise, references to commercial tools which provide them are linked.

References

1. nicolasbize.com/blog/the-best-ide-in-the-world
2. The von Neumann syndrome and the CS education dilemma
3. The tunnel vision syndrome: Massively delaying progress
4. fpl.uni-kl.de/staff/hartenstein/lot/Invent_something.htm
5. wiring.org.co
6. arduino.cc
7. arduinohistory.github.io
8. atmel.com/products/microcontrollers/avr/megaavr.aspx
9. microchip.com/pagehandler/en-us/products/picmicrocontrollers
10. beagleboard.org
11. raspberrypi.org
12. kickstarter: 1598272670/chip-the-worlds-first-9-computer
13. kickstarter: 1106670630/mojo-digital-design-for-the-hobbyist
14. kickstarter: 1575992013/logi-fpga-development-board-for-raspberry-pi-beagl
15. xilinx.com/products/silicon-devices/fpga/spartan-6
16. hackaday.io/project/38-arduino-compatible-fpga-shield
17. freerangefactory.org/site/pmwiki.php/Main/Hardware
18. fpgadeveloper.com/2014/03/comparison-of-zynq-boards
19. xilinx.com/products/silicon-devices/soc/zynq-7000
20. latticesemi.com/icestick
21. latticesemi.com/Products/DevelopmentBoardsAndKits/iCE40HX8KBreakoutBoard
22. fpgalibre.sourceforge.net/Kefir
23. icoboard.org/about-icoboard
24. nandland.com/goboard
25. github.com/FPGAwars/icezum
26. latticesemi.com/en/Products/FPGAandCPLD/iCE40
27. en.wikipedia.org/wiki/Gratis_versus_libre

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Distribution

• @elide
• @vhdl-base
  • GHDL: VHDL 2008/93/87 simulator.
    • ghdlsynth-beta
  • GtkWave: GTK+ based wave viewer for Unix, Win32, and Mac OSX which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files.
• @vhdl-ext
  • VUnit: open source unit testing framework for VHDL/SystemVerilog written in Python.
  • OSVVM: Open Source VHDL Verification Methodology.
  • GitHub:UVVM: Universal VHDL Verification Methodology.
  • GitHub:potentialventures/cocotb: Coroutine Co-simulation Test Bench library for writing VHDL and Verilog testbenches in Python.
• @verilog
  • iverilog: a Verilog simulation and synthesis tool that operates as a compiler, compiling source code written in Verilog (IEEE-1364) into some target format.
  • Project Icestorm
    • icestorm: aims at reverse engineering and documenting the bitstream format of Lattice iCE40 FPGAs and providing simple tools for analyzing and creating bitstream files.
    • arachne-pnr: open source Place and Route tool for FPGAs.
    • yosys: an open source framework for Verilog RTL synthesis.
  • Required by yosys:
    • graphviz: open source graph (network) visualization project.
    • pypi/xdot: interactive viewer for Graphviz dot files.
  • mhdlsim: combine iverilog and ghdl.