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Fixed autoinstantiation tripping on brackets and unpacked dimensions #198

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merged 5 commits into from
Jan 5, 2024

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richzwart
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This should fix issue #168 where mdule instantiation cannot handle port arrays.

Additionally I found that the auto-instantiation will trip up on any expressions being included in port sizes or parameter defaults when they include the end brace ')'

module example #(parameter P_DATA_WIDTH = (8)) (
input wire clk,
input wire [P_DATA_WIDTH-1:0] data [1:0]
);
// something here
endmodule

Great work on this plugin!

@joecrop
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joecrop commented Aug 8, 2023

Thanks so much for your contribution @richzwart. Can you please add a test case or two here: https://github.com/eirikpre/VSCode-SystemVerilog/blob/master/src/test/ModuleInstantiator.test.ts ?

@joecrop joecrop self-requested a review January 5, 2024 18:57
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2 participants