JLR Chiplet Challenge, Inter IIT 12.0

This is the official project repository for Inter IIT 12.0's JLR Chiplet Challenge Problem Statement from Electronics Club, IIT Guwahati.

Reports & Presentation

Please refer to Mid-submission Report, Final Report and Presentation within this repo to access the project reports & final presentation.

Project Files

• /MATLAB_Files contains MATLAB simulation files
• /Thermal_Submission contains the thermal simulation results
• /RapidChiplet_Simulation_Results contains RapidChiplet simulation results
• /Synthesis_Report contains synthesis results of our neural accelerator and risc chip designs across multiple processes
• /Verilog_Files contains verilog source code files

Inter IIT Results

We were ranked 4th overall in the Problem Statement, barely missing podium.