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v1.1 changelog #6

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gkasprow opened this issue Jun 13, 2021 · 0 comments

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gkasprow commented Jun 13, 2021

Added startup circuit to the VCXO
Problematic bidirectional level translators were replaced with fixed-direction ones
Added missing TVDD18 symbol pin
Added LD7 pull-down
Negative rail converter supply switched to 12V rail
Added assembly option for IDX_IN. Now the signal can be sourced from CLK2_BIDIR. This enables possibility of routing all clock and sync signals through the mTCA backplane

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