Add initial register mapping for STM32 F1 AFIO and FLASH

[mryndzionek]

Added just the register needed for STM32 F1 support in Embassy. Not sure if afio_f1 should be afio_v1 (AFIO is needed for EXTI control for gpio_v1, so renaming probably makes sense).

[Dirbaio]

Thanks for the PR!

The only issue I see is FLASH register block is not complete though. We shouldn't have incomplete blocks, as it can create confusion.

You can extract them automatically from SVD files following the instructions here.

Not sure if afio_f1 should be afio_v1 (AFIO is needed for EXTI control for gpio_v1, so renaming probably makes sense).

AFIO only exists on F1 anyway, so either is fine, I guess

[mryndzionek]

Okay, I updated the FLASH registers. I also noticed that AFIO is not mutually consistent (ties probably with #10).

[Dirbaio]

Thank you!

I also noticed that AFIO is not mutually consistent (ties probably with #10).

True... It seems they're all "compatible" in the sense that a given bit is either present or not present, but it never does X in one chip and Y in another chip. It's like the RCC's. In this case what we've done is "merge" all the yamls to obtain a single one with all the bits, that works for all the chips in the family. The merge_regs.py script does this.

#10 is about adding info on the YAMLs about pinouts. Something like "peripehral X with remap=0 uses pins XXX, with remap=1 uses pins YYY". Since it works differently than all the other stm32 families it'll need a new YAML format.

This info is then used in embassy-stm32 to autogenerate the trait implementations to enforce correct pins when creating an UART etc.

[mryndzionek]

Okay, so I think I need to re-generate AFIO yaml. The one here was done manually. Do you want me to do this while I'm at it?

[Dirbaio]

Sure, why not! :)

[mryndzionek]

Okay, PR #87