ARM: dts: imx28: fix enet flapping issue

The net system is (intentionally) designed to only ever issue
a hardware reset once. While there have been some hacks over the
years to try and bring in a runtime PHY reset control, for example
to reduce power by turning everything off when the interface is down;
these are unused by many drivers and look to be slowly ripped out over
time.

The FEC driver, while aware of the imx28 ENET_CLK out, still ends
up turning it off at points. Because of the above design choice to
only ever reset once, this means the PHY has its clock turned off
and back on without a real reset. And in the case of the imx28 MAC,
this defaults to 25 MHz, then goes to 50 MHz, when there is a MAC
restart.

By connecting the enet-out clock to the ethphy handle, this gets
connected to the PHY driver which never turns it off. This keeps the
clock refcount always positive, and the clock will never turn off.

Testing has shown this to eliminate the ethernet PHY link
cycling/flapping issue on out i.MX28 platforms.

Signed-off-by: Kris Bahnsen <kris@embeddedTS.com>

arch/arm/boot/dts/imx28-ts7400v2.dts

@@ -200,7 +200,7 @@
 	phy-supply = <&reg_enet_3v3>;
 	phy-handle = <&ethphy0>;
 	phy-reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
-	phy-reset-duration = <26>;
+	phy-reset-duration = <100>;
 	phy-reset-post-delay = <1>;
 	status = "okay";
 
@@ -210,6 +210,9 @@
 
 		ethphy0: ethernet-phy@0 {
 			compatible = "ethernet-phy-ieee802.3-c22";
+			/* magic number "64" is enet out from CPU */
+			clocks = <&clks 64>;
+			clock-names = "rmii-ref";
 			reg = <0>;
 		};
 	};

arch/arm/boot/dts/imx28-ts7670.dts

@@ -228,7 +228,7 @@
 	phy-supply = <&reg_enet_3v3>;
 	phy-handle = <&ethphy0>;
 	phy-reset-gpios = <&gpio2 9 GPIO_ACTIVE_LOW>;
-	phy-reset-duration = <26>;
+	phy-reset-duration = <100>;
 	phy-reset-post-delay = <1>;
 	status = "okay";
 
@@ -238,6 +238,9 @@
 
 		ethphy0: ethernet-phy@0 {
 			compatible = "ethernet-phy-ieee802.3-c22";
+			/* magic number "64" is enet out from CPU */
+			clocks = <&clks 64>;
+			clock-names = "rmii-ref";
 			reg = <0>;
 		};
 	};