serwb/demo: Add CPU to ecpix5 and remove uartbone.

enjoy-digital · Feb 20, 2024 · 39824a4 · 39824a4
1 parent 124c573
commit 39824a4
Showing 1 changed file with 10 additions and 7 deletions.
diff --git a/bench/serwb/demo/ecpix5.py b/bench/serwb/demo/ecpix5.py
@@ -43,7 +43,7 @@
 
 # SerWBDemoSoC ------------------------------------------------------------------------------------
 
-class SerWBDemoSoC(SoCMini):
+class SerWBDemoSoC(SoCCore):
     def __init__(self, platform, with_analyzer=False):
         sys_clk_freq = int(25e6)
 
@@ -52,14 +52,17 @@ def __init__(self, platform, with_analyzer=False):
 
         # SoCMini ----------------------------------------------------------------------------------
         SoCMini.__init__(self, platform, sys_clk_freq,
-            csr_data_width = 32,
-            ident          = "LiteICLink SerWB demo on ECPIX-5",
-            ident_version  = True,
+            csr_data_width       = 32,
+            cpu_type             = "vexriscv",
+            integrated_rom_size  = 0x10000,
+            integrated_sram_size = 0x10000,
+            with_timer           = True,
+            ident                = "LiteICLink SerWB demo on ECPIX-5",
+            ident_version        = True,
+            with_uart            = True,
+            uart_name            = "crossover",
         )
 
-        # UARTBone ---------------------------------------------------------------------------------
-        self.add_uartbone()
-
         # Etherbone --------------------------------------------------------------------------------
         self.ethphy = LiteEthPHYRGMII(
             clock_pads = self.platform.request("eth_clocks"),