Compatibility with Zynq7000 FPGAs (#19)

enjoy-digital · May 26, 2024 · b3ccc51 · b3ccc51
1 parent f492a65
commit b3ccc51
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/liteiclink/serwb/phy.py b/liteiclink/serwb/phy.py
@@ -408,7 +408,7 @@ def __init__(self, device, pads, mode="master", init_timeout=2**16, clk="sys", c
             assert clk_ratio == "1:1"
             taps = 512
             self.serdes = KUSerdes(pads, mode)
-        elif device[:4] == "xc7a":
+        elif device[:4] in ["xc7a", "xc7z"]:
             assert clk_ratio == "1:1"
             taps = 32
             self.serdes = S7Serdes(pads, mode)