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bench/serwb: Minor cleanup and updates.
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@enjoy-digital
enjoy-digital committed Feb 28, 2024
1 parent 0e18f46 commit bf1ed90
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Showing 8 changed files with 297 additions and 207 deletions.
65 changes: 41 additions & 24 deletions bench/serwb/icebreaker.py
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
#
# This file is part of LiteICLink.
#
# Copyright (c) 2020-2023 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2020-2024 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause

import argparse
Expand Down Expand Up @@ -65,7 +65,8 @@ def __init__(self, platform, loopback=False, with_analyzer=False):
ident = "LiteICLink SerWB bench on iCEBreaker",
ident_version = True,
with_uart = True,
uart_name = "uartbone")
uart_name = "uartbone",
)

# SerWB ------------------------------------------------------------------------------------
# SerWB simple test with a SerWB Master added as a Slave peripheral to the SoC and connected
Expand All @@ -79,43 +80,59 @@ def __init__(self, platform, loopback=False, with_analyzer=False):
# +--------+ +------+ +------+ +------+
# ------------------------------------------------------------------------------------------

# Pads
# Pads.
# -----
if loopback:
serwb_master_pads = Record([("tx", 1), ("rx", 1)])
serwb_slave_pads = Record([("tx", 1), ("rx", 1)])
self.comb += serwb_slave_pads.rx.eq(serwb_master_pads.tx)
self.comb += serwb_master_pads.rx.eq(serwb_slave_pads.tx)
self.comb += [
serwb_slave_pads.rx.eq(serwb_master_pads.tx),
serwb_master_pads.rx.eq(serwb_slave_pads.tx),
]
else:
serwb_master_pads = platform.request("serwb_master")
serwb_slave_pads = platform.request("serwb_slave")

# Master
# Master.
# -------
self.serwb_master_phy = SERWBPHY(
device = platform.device,
pads = serwb_master_pads,
mode = "master")
mode = "master",
)

# Slave
# Slave.
# ------
self.serwb_slave_phy = SERWBPHY(
device = platform.device,
pads = serwb_slave_pads,
mode ="slave")

# Wishbone Slave
serwb_master_core = SERWBCore(self.serwb_master_phy, self.clk_freq, mode="slave",
mode ="slave",
)

# Wishbone Slave.
# ---------------
self.serwb_master_core = serwb_master_core = SERWBCore(
phy = self.serwb_master_phy,
clk_freq = self.clk_freq,
mode = "slave",
etherbone_buffer_depth = 1,
tx_buffer_depth = 0,
rx_buffer_depth = 0)
self.submodules += serwb_master_core

# Wishbone Master
serwb_slave_core = SERWBCore(self.serwb_slave_phy, self.clk_freq, mode="master",
rx_buffer_depth = 0,
)

# Wishbone Master.
# ----------------
self.serwb_slave_core = serwb_slave_core = SERWBCore(
phy = self.serwb_slave_phy,
clk_freq = self.clk_freq,
mode = "master",
etherbone_buffer_depth = 1,
tx_buffer_depth = 0,
rx_buffer_depth = 0)
self.submodules += serwb_slave_core
rx_buffer_depth = 0,
)

# Wishbone SRAM
# Wishbone SRAM.
# --------------
self.serwb_sram = Up5kSPRAM(size=64*kB)
self.bus.add_slave("serwb", serwb_master_core.bus, SoCRegion(origin=0x30000000, size=8192))
self.comb += serwb_slave_core.bus.connect(self.serwb_sram.bus)
Expand All @@ -131,10 +148,10 @@ def __init__(self, platform, loopback=False, with_analyzer=False):
# Build --------------------------------------------------------------------------------------------

def main():
parser = argparse.ArgumentParser(description="LiteICLink SerWB bench on iCEBreaker")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM)")
parser.add_argument("--loopback", action="store_true", help="Loopback SerWB in FPGA (no IOs)")
parser = argparse.ArgumentParser(description="LiteICLink SerWB bench on iCEBreaker.")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM).")
parser.add_argument("--loopback", action="store_true", help="Loopback SerWB in FPGA (no IOs).")
args = parser.parse_args()

platform = icebreaker.Platform()
Expand Down
67 changes: 44 additions & 23 deletions bench/serwb/nexys_video.py
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,7 @@
#
# This file is part of LiteICLink.
#
# Copyright (c) 2017-2023 Florent Kermarrec <florent@enjoy-digital.fr>
# Copyright (c) 2017-2024 Florent Kermarrec <florent@enjoy-digital.fr>
# SPDX-License-Identifier: BSD-2-Clause

import argparse
Expand Down Expand Up @@ -32,7 +32,7 @@
# IOs ----------------------------------------------------------------------------------------------

serwb_io = [
# HDMI loopback
# HDMI loopback.
("serwb_master", 0,
Subsignal("clk_p", Pins("T1"), IOStandard("TMDS_33")), # hdmi_out clk
Subsignal("clk_n", Pins("U1"), IOStandard("TMDS_33")), # hdmi_out clk
Expand Down Expand Up @@ -63,13 +63,17 @@ def __init__(self, platform, sys_clk_freq):

# # #

# PLL.
# ----
self.pll = pll = S7PLL(speedgrade=-1)
self.comb += pll.reset.eq(~platform.request("cpu_reset"))
pll.register_clkin(platform.request("clk100"), 100e6)
pll.create_clkout(self.cd_sys, sys_clk_freq)
pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq)
pll.create_clkout(self.cd_idelay, 200e6)

# IDelayCtrl.
# -----------
self.idelayctrl = S7IDELAYCTRL(self.cd_idelay)

# SerWBTestSoC ------------------------------------------------------------------------------------
Expand All @@ -92,7 +96,8 @@ def __init__(self, platform, low_speed=True, with_analyzer=True):
ident = "LiteICLink SerWB bench on Nexys Video",
ident_version = True,
with_uart = True,
uart_name = "uartbone")
uart_name = "uartbone",
)

# SerWB ------------------------------------------------------------------------------------
# SerWB simple test with a SerWB Master added as a Slave peripheral to the SoC and connected
Expand All @@ -106,32 +111,48 @@ def __init__(self, platform, low_speed=True, with_analyzer=True):
# +--------+ +------+ +------+ +------+
# ------------------------------------------------------------------------------------------

# Enable
# Enable.
# -------
self.comb += platform.request("serwb_enable").eq(1)

# PHY.
# ----
phy_cls = SERWBLowSpeedPHY if low_speed else SERWBPHY

# Master
# Master.
# -------
self.serwb_master_phy = phy_cls(
device = platform.device,
pads = platform.request("serwb_master"),
mode = "master")
mode = "master",
)

# Slave
# Slave.
# ------
self.serwb_slave_phy = phy_cls(
device = platform.device,
pads = platform.request("serwb_slave"),
mode ="slave")

# Wishbone Slave
serwb_master_core = SERWBCore(self.serwb_master_phy, self.clk_freq, mode="slave")
self.submodules += serwb_master_core

# Wishbone Master
serwb_slave_core = SERWBCore(self.serwb_slave_phy, self.clk_freq, mode="master")
self.submodules += serwb_slave_core

# Wishbone SRAM
mode ="slave",
)

# Wishbone Slave.
# ---------------
self.serwb_master_core = serwb_master_core = SERWBCore(
phy = self.serwb_master_phy,
clk_freq = self.clk_freq,
mode = "slave",
)

# Wishbone Master.
# ----------------
self.serwb_slave_core = serwb_slave_core = SERWBCore(
phy = self.serwb_slave_phy,
clk_freq = self.clk_freq,
mode = "master",
)

# Wishbone SRAM.
# --------------
self.serwb_sram = wishbone.SRAM(8192)
self.bus.add_slave("serwb", serwb_master_core.bus, SoCRegion(origin=0x30000000, size=8192))
self.comb += serwb_slave_core.bus.connect(self.serwb_sram.bus)
Expand Down Expand Up @@ -170,11 +191,11 @@ def __init__(self, platform, low_speed=True, with_analyzer=True):
# Build --------------------------------------------------------------------------------------------

def main():
parser = argparse.ArgumentParser(description="LiteICLink SerWB bench on Nexys Video")
parser.add_argument("--build", action="store_true", help="Build bitstream")
parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM)")
parser.add_argument("--low-speed", action="store_true", help="Use Low-Speed PHY")
parser.add_argument("--with-analyzer", action="store_true", help="Add LiteScope Analyzer")
parser = argparse.ArgumentParser(description="LiteICLink SerWB bench on Nexys Video.")
parser.add_argument("--build", action="store_true", help="Build bitstream.")
parser.add_argument("--load", action="store_true", help="Load bitstream (to SRAM).")
parser.add_argument("--low-speed", action="store_true", help="Use Low-Speed PHY.")
parser.add_argument("--with-analyzer", action="store_true", help="Add LiteScope Analyzer.")
args = parser.parse_args()

platform = digilent_nexys_video.Platform()
Expand Down

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