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serdes: Cleanup instances now that we are no longer limited to 255 pa…
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…rameters with python 3.7+.
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@enjoy-digital
enjoy-digital committed Jan 18, 2024
1 parent 030e96c commit f381adf
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Showing 5 changed files with 143 additions and 170 deletions.
26 changes: 10 additions & 16 deletions liteiclink/serdes/gth3_ultrascale.py
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Original file line number Diff line number Diff line change
Expand Up @@ -751,16 +751,13 @@ def __init__(self, pll, tx_pads, rx_pads, sys_clk_freq, tx_clk=None, rx_clk=None
p_TX_SARC_LPBK_ENB = 0b0,
p_USE_PCS_CLK_PHASE_SEL = 0b0,
p_WB_MODE = 0b00,
)

self.gth_params.update(
p_CLK_COR_MAX_LAT = 12 if rx_buffer_enable else 20,
p_CLK_COR_MIN_LAT = 8 if rx_buffer_enable else 18,
p_CPLL_FBDIV = 1 if (use_qpll0 | use_qpll1) else pll.config["n2"],
p_CPLL_FBDIV_45 = 4 if (use_qpll0 | use_qpll1) else pll.config["n1"],
p_CPLL_REFCLK_DIV = 1 if (use_qpll0 | use_qpll1) else pll.config["m"],
)
self.gth_params.update(

p_RXBUF_EN = "TRUE" if rx_buffer_enable else "FALSE",
p_RXBUF_THRESH_OVFLW = 57 if rx_buffer_enable else 0,
p_RXBUF_THRESH_OVRD = "TRUE" if rx_buffer_enable else "FALSE",
Expand All @@ -769,16 +766,13 @@ def __init__(self, pll, tx_pads, rx_pads, sys_clk_freq, tx_clk=None, rx_clk=None
p_RX_DATA_WIDTH = data_width,
p_RX_INT_DATAWIDTH = data_width == 40,
p_RX_XCLK_SEL = "RXDES" if rx_buffer_enable else "RXUSR",
)
self.gth_params.update(

p_TXBUF_EN = "TRUE" if tx_buffer_enable else "FALSE",
p_TXOUT_DIV = pll.config["d"],
p_TX_DATA_WIDTH = data_width,
p_TX_INT_DATAWIDTH = data_width == 40,
p_TX_XCLK_SEL = "TXOUT" if tx_buffer_enable else "TXUSR",
)

self.gth_params.update(
# Reset modes
i_RESETOVRD = 0,
i_GTRESETSEL = 0,
Expand Down Expand Up @@ -870,13 +864,13 @@ def __init__(self, pll, tx_pads, rx_pads, sys_clk_freq, tx_clk=None, rx_clk=None
i_RXUSRCLK2 = ClockSignal("rx"),

# RX Byte and Word Alignment Ports
o_RXBYTEISALIGNED = Open(),
o_RXBYTEREALIGN = Open(),
o_RXCOMMADET = Open(),
i_RXCOMMADETEN = 1,
i_RXMCOMMAALIGNEN = (~clock_aligner & self.rx_align & (rx_prbs_config == 0b00)) if rx_buffer_enable else 0,
i_RXPCOMMAALIGNEN = (~clock_aligner & self.rx_align & (rx_prbs_config == 0b00)) if rx_buffer_enable else 0,
i_RXSLIDE = 0,
o_RXBYTEISALIGNED = Open(),
o_RXBYTEREALIGN = Open(),
o_RXCOMMADET = Open(),
i_RXCOMMADETEN = 1,
i_RXMCOMMAALIGNEN = (~clock_aligner & self.rx_align & (rx_prbs_config == 0b00)) if rx_buffer_enable else 0,
i_RXPCOMMAALIGNEN = (~clock_aligner & self.rx_align & (rx_prbs_config == 0b00)) if rx_buffer_enable else 0,
i_RXSLIDE = 0,

# RX data
o_RXCTRL0 = Cat(*[rxdata[10*i+8] for i in range(nwords)]),
Expand All @@ -895,7 +889,7 @@ def __init__(self, pll, tx_pads, rx_pads, sys_clk_freq, tx_clk=None, rx_clk=None
i_GTHRXP = rx_pads.p,
i_GTHRXN = rx_pads.n,
o_GTHTXP = tx_pads.p,
o_GTHTXN = tx_pads.n
o_GTHTXN = tx_pads.n,
)

# TX clocking ------------------------------------------------------------------------------
Expand Down
10 changes: 2 additions & 8 deletions liteiclink/serdes/gth4_ultrascale.py
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Original file line number Diff line number Diff line change
Expand Up @@ -899,16 +899,13 @@ def __init__(self, pll, tx_pads, rx_pads, sys_clk_freq, tx_clk=None, rx_clk=None
p_USB_U2_SAS_MIN_COM = 36,
p_USE_PCS_CLK_PHASE_SEL = 0b0,
p_Y_ALL_MODE = 0b0,
)

self.gth_params.update(
p_CLK_COR_MAX_LAT = 12 if rx_buffer_enable else 20,
p_CLK_COR_MIN_LAT = 8 if rx_buffer_enable else 18,
p_CPLL_FBDIV = 1 if (use_qpll0 | use_qpll1) else pll.config["n2"],
p_CPLL_FBDIV_45 = 4 if (use_qpll0 | use_qpll1) else pll.config["n1"],
p_CPLL_REFCLK_DIV = 1 if (use_qpll0 | use_qpll1) else pll.config["m"],
)
self.gth_params.update(

p_RXBUF_EN = "TRUE" if rx_buffer_enable else "FALSE",
p_RXBUF_THRESH_OVFLW = 57 if rx_buffer_enable else 0,
p_RXBUF_THRESH_OVRD = "TRUE" if rx_buffer_enable else "FALSE",
Expand All @@ -917,16 +914,13 @@ def __init__(self, pll, tx_pads, rx_pads, sys_clk_freq, tx_clk=None, rx_clk=None
p_RX_DATA_WIDTH = data_width,
p_RX_INT_DATAWIDTH = data_width == 40,
p_RX_XCLK_SEL = "RXDES" if rx_buffer_enable else "RXUSR",
)
self.gth_params.update(

p_TXBUF_EN = "TRUE" if tx_buffer_enable else "FALSE",
p_TXOUT_DIV = pll.config["d"],
p_TX_DATA_WIDTH = data_width,
p_TX_INT_DATAWIDTH = data_width == 40,
p_TX_XCLK_SEL = "TXOUT" if tx_buffer_enable else "TXUSR",
)

self.gth_params.update(
# Reset modes
i_RESETOVRD = 0,

Expand Down
5 changes: 2 additions & 3 deletions liteiclink/serdes/gtp_7series.py
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Original file line number Diff line number Diff line change
Expand Up @@ -579,9 +579,8 @@ def __init__(self, qpll, tx_pads, rx_pads, sys_clk_freq, qpll_reset=True, tx_clk
# TX Buffer Attributes
p_TXSYNC_MULTILANE = 0b0,
p_TXSYNC_OVRD = 0b1 if tx_buffer_enable else 0b0,
p_TXSYNC_SKIP_DA = 0b0
)
self.gtp_params.update(
p_TXSYNC_SKIP_DA = 0b0,

# CPLL Ports
i_GTRSVD = 0b0000000000000000,
i_PCSRSVDIN = 0b0000000000000000,
Expand Down
5 changes: 2 additions & 3 deletions liteiclink/serdes/gtx_7series.py
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Original file line number Diff line number Diff line change
Expand Up @@ -593,9 +593,8 @@ def __init__(self, pll, tx_pads, rx_pads, sys_clk_freq, tx_clk=None, rx_clk=None
p_RX_DFE_XYD_CFG = 0b0000000000000,

# TX Configurable Driver Attributes
p_TX_PREDRIVER_MODE = 0b0
)
self.gtx_params.update(
p_TX_PREDRIVER_MODE = 0b0,

# CPLL Ports
o_CPLLFBCLKLOST = Open(),
o_CPLLLOCK = Signal() if use_qpll else pll.lock,
Expand Down

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