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WIP: Serwb improvements #13

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@cklarhorst cklarhorst commented May 15, 2023

I decided to make this PR bigger:

My open todos:

  • Wait for PR serwb: Fix shifting #14
  • s7serdes: Add Virtex7 support
  • s7serdes: Allow different serdes data_width options (4,6,8 bits wide)
  • s7serdes: Allow serdes width expansion (10,14 bits)
  • s7serdes: Allow support for single ended IO
  • Add s6serdes implementation(2,4 bits wide)

Current additional ideas:

  • s6serdes: Improve the idelay2 range: Use 255 taps for edge detection and just make sure that the delay used is less than the errdata value.

What was tested (sync + memtest over serwb, all with PR#14):

  • s7serdes: Virtex7-Virtex7 on custom board (8bit mode, lvds, with s7serdes clocking module, 100mhz sysclk)
  • s7serdes: Kintex7-Virtex7 on custom board (4/8bit mode, lvds, shared main clk, 100mhz sysclk)
  • s7serdes: Kintex7-Virtex7 on custom board (10bit mode, lvds, shared main clk)
  • s7serdes: Virtex7-Virtex7 on custom board (10bit mode, lvds, with s7serdes clocking module)
  • s6serdes: Spartan6-Spartan6 (2/4bit, lvcmos33, with S6SerdesClockingSimple, 50mhz sysclk) -> does only sync with taps override to 255 (final delay was in errdata accepted range)

As always, thank you for this great project.
Let me know if there is anything I can improve or do differently to reduce work on your side.

@cklarhorst cklarhorst changed the title s7serdes: Make s7serdes data_width configurable WIP: s7serdes: Make s7serdes data_width configurable May 26, 2023
@cklarhorst cklarhorst force-pushed the s7serdes_configurable_width branch from bcfe441 to 25d5fcb Compare May 30, 2023 15:49
@cklarhorst cklarhorst changed the title WIP: s7serdes: Make s7serdes data_width configurable WIP: Serwb improvements May 30, 2023
# https://support.xilinx.com/s/article/38408?language=en_US
max_taps = {188: 107, 200: 101, 266:72, 333: 54, 400: 43, 533: 28, 625: 22,
667: 20, 800: 14, 945: 9, 1000: 8, 1050: 7, 1080: 6}
sys_freq = 50 # todo: how to get that information?
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@cklarhorst cklarhorst May 30, 2023

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Does somebody know a good way to get the sysfreq, or is it ok to make it a parameter?

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Hi @cklarhorst,

that's indeed a point I want to improve and avoid having to pass sys_clk_freq parameter to all module that require it. (ie having access to it globally when elaborating a design). I'll try to work on such improvements in the future, but for now for this module, if sys_clk_freq is required, you can add an argument (and make it optional with a default value of None).

@enjoy-digital
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Hi @cklarhorst,

thanks for your work, this is really interesting and the changes look good. #14 is now merged and happy to do a closer review of this PR when you think it will be ready.

@cklarhorst
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Thanks. (I have to change my focus for a month, so I will finish this PR sometime at the end of next month.)

@enjoy-digital
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@cklarhorst Sure, no problem.

Bit widths of 4,6,8 are supported for non cascaded serdese2 in ddr mode.
Note that a width of 6 is currently useless because it is not supported by the stream converter.
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