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Reduce number of classical instruction edges in InstructionBlock::graph #1

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merged 5 commits into from
Dec 20, 2023

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@erichulburd erichulburd commented Dec 19, 2023

The ultimate goal of this PR is to simplify the InstructionBlock::graph and thereby improve the ability of a hardware scheduler to schedule a Quil program by reducing the number of edges between classical instructions and block start/end.

Two types of edges in the InstructionBlock::graph are deemed extraneous in this work:

  1. An edge from two consecutive classical instructions that read from / write to different memory regions. Rather than insist on classical instruction execute in the particular order they are written in a Quil program, only represent ordering of classical Quil instructions based upon the memory regions they read and write to (this is already done with MemoryAccessQueue).
  2. Edges from BlockStart, if the node has other incoming edges, or to BlockEnd, if the node has other outgoing edges. Note that while this could apply equally to InstructionRole::RfControl, this change set deliberately only impacts edges to and from classical instructions.
DECLARE params1 REAL[10]
DECLARE params2 REAL[10]
DECLARE params3 REAL[10]
DECLARE params4 REAL[10]
DECLARE integer1 INTEGER[10]

LOAD params1[0] params2 integers[0] # LOAD_1 in graphs below
SHIFT-PHASE 0 "rf" params1[0]
LOAD params3[0] params4 integers[0] # LOAD_2 in graphs below

Old representation of InstructionBlock::graph.

flowchart TD
    BlockStart --> LOAD_1
    BlockStart --> RZ
    LOAD_1 --> RZ
    LOAD_1 --> LOAD_2
    LOAD_1 --> BlockEnd
    LOAD_2 --> BlockEnd
    RZ --> BlockEnd
Loading

In the original algorithm, there is an edge from LOAD_1 to BlockEnd because there are pending on params1 and integers.

New representation of InstructionBlock::graph.

flowchart TD
    BlockStart --> LOAD_1
    BlockStart --> LOAD_2
    LOAD_1 --> RZ
    LOAD_2 --> BlockEnd
    RZ --> BlockEnd
Loading

There are three invariants of the InstructionBlock::graph that remain unchanged:

  1. There is always a path connecting the BlockStart to any node in the graph.
  2. There is always a path connecting any node in the graph to the BlockEnd.
  3. These invariants pertain to the BlockStart and BlockEnd as well. In other words, there is always a connecting path from the BlockStart to the BlockEnd regardless as to whether there are any instructions in the block.

TODO:

  • self-review.

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github-actions bot commented Dec 20, 2023

PR Preview Action v1.4.6
🚀 Deployed preview to https://erichulburd.github.io/quil-rs/pr-preview/pr-1/
on branch quil-py-docs at 2023-12-20 01:14 UTC

@erichulburd erichulburd force-pushed the relax_classical_memory_constraints branch from 2c6147f to cfc2fb1 Compare December 20, 2023 00:37
@erichulburd erichulburd changed the title Reduce number of edges in InstructionBlock::graph Reduce number of classical instruction edges in InstructionBlock::graph Dec 20, 2023
@erichulburd erichulburd merged commit 7dc0e6c into main Dec 20, 2023
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@erichulburd erichulburd deleted the relax_classical_memory_constraints branch December 20, 2023 01:14
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