refactor: remove empty folders, start docs improvements

README.md

@@ -111,6 +111,19 @@ npm install --save-dev @commitlint/{config-conventional,cli}
 sudo apt install ghdl
 ```
 
+### Project Structure
+
+All packages and modules fall into one of three main categories and can thus be found in the corresponding package
+
+ - `elasticai.creator.nn`: contains trainable modules that can be translated to vhdl to build a hardware accelerator
+ - `elasticai.creator.base_modules`: contains shared functionality and data structures, that we use to create our neural network software modules
+ - `elasticai.creator.vhdl`: contains shared code that we use to represent and generate vhdl files
+
+#### Note
+I think actually we have four categories: A) generate vhdl, B) define pytorch/mlframework modules, C) generate files and fill templates, D) combine the three to create translatable modules
+
+Below we go into more detail on each of these packages
+
 
 ### Conventional Commit Rules
 
@@ -129,32 +142,6 @@ We use conventional commits (see [here](https://www.conventionalcommits.org/en/v
 | perf         |                |
 
 
-### Adding new translation targets
-
-New translation targets should be located in their own folder, e.g. vhdl for translating from any language to vhdl.
-Workflow for adding a new translation:
-1. Obtain a structure, such as a list in a sequential case, which will describe the connection between every component.
-2. Identify and label relevant structures, in the base cases it can be simply separate layers.
-3. Map each structure to its function which will convert it.
-4. Do such conversions.
-5. Recreate connections based on 1.
-
-Each sub-step should be separable and it helps for testing if common functions are wrapped around an adapter.
-
-
-### Syntax Checking
-
-[GHDL](https://ghdl.github.io/ghdl/) supports a [syntax checking](https://umarcor.github.io/ghdl/using/InvokingGHDL.html#check-syntax-s) which checks the syntax of a vhdl file without generating code.
-The command is as follows:
-```bash
-ghdl -s path/to/vhdl/file
-```
-For checking all vhdl files together in our project we can just run:
-```bash
-ghdl -s elasticai/creator/**/*.vhd
-```
-
-
 ### Tests
 
 Our implementation is tested with unit and integration.

elasticai/creator/nn/conv1d/design.py

@@ -5,8 +5,8 @@
     InProjectTemplate,
     module_to_package,
 )
-from elasticai.creator.vhdl.design_base.design import Design
-from elasticai.creator.vhdl.design_base.ports import Port
+from elasticai.creator.vhdl.design.design import Design
+from elasticai.creator.vhdl.design.ports import Port
 from elasticai.creator.vhdl.designs.rom import Rom
 from elasticai.creator.vhdl.savable import Path
 

elasticai/creator/nn/conv1d/layer.py

@@ -9,7 +9,7 @@
 from elasticai.creator.base_modules.two_complement_fixed_point_config import (
     FixedPointConfig,
 )
-from elasticai.creator.vhdl.design_base.design import Design
+from elasticai.creator.vhdl.design.design import Design
 from elasticai.creator.vhdl.translatable import Translatable
 
 from .design import FPConv1d as FPConv1dDesign

elasticai/creator/nn/hard_sigmoid/design.py

@@ -3,7 +3,7 @@
     InProjectTemplate,
     module_to_package,
 )
-from elasticai.creator.vhdl.design_base.design import Design, Port
+from elasticai.creator.vhdl.design.design import Design, Port
 from elasticai.creator.vhdl.savable import Path
 
 

elasticai/creator/nn/hard_sigmoid/layer.py

@@ -2,7 +2,7 @@
 from elasticai.creator.base_modules.two_complement_fixed_point_config import (
     FixedPointConfig,
 )
-from elasticai.creator.vhdl.design_base.design import Design
+from elasticai.creator.vhdl.design.design import Design
 from elasticai.creator.vhdl.translatable import Translatable
 
 from .design import FPHardSigmoid as FPHardSigmoidDesign

elasticai/creator/nn/hard_tanh/design.py

@@ -3,7 +3,7 @@
     InProjectTemplate,
     module_to_package,
 )
-from elasticai.creator.vhdl.design_base.design import Design, Port
+from elasticai.creator.vhdl.design.design import Design, Port
 from elasticai.creator.vhdl.savable import Path
 
 

elasticai/creator/nn/hard_tanh/layer.py

@@ -2,7 +2,7 @@
 from elasticai.creator.base_modules.two_complement_fixed_point_config import (
     FixedPointConfig,
 )
-from elasticai.creator.vhdl.design_base.design import Design
+from elasticai.creator.vhdl.design.design import Design
 from elasticai.creator.vhdl.translatable import Translatable
 
 from .design import FPHardTanh as FPHardTanhDesign

elasticai/creator/nn/identity/design.py

@@ -4,8 +4,8 @@
     InProjectTemplate,
     module_to_package,
 )
-from elasticai.creator.vhdl.design_base.design import Design
-from elasticai.creator.vhdl.design_base.ports import Port
+from elasticai.creator.vhdl.design.design import Design
+from elasticai.creator.vhdl.design.ports import Port
 from elasticai.creator.vhdl.savable import Path
 
 

elasticai/creator/nn/identity/layer.py

@@ -1,5 +1,5 @@
 from elasticai.creator.base_modules.identity import Identity
-from elasticai.creator.vhdl.design_base.design import Design
+from elasticai.creator.vhdl.design.design import Design
 from elasticai.creator.vhdl.translatable import Translatable
 
 from .design import BufferedIdentity as IdentityDesign

elasticai/creator/nn/linear/design.py

@@ -6,8 +6,8 @@
     InProjectTemplate,
     module_to_package,
 )
-from elasticai.creator.vhdl.design_base.design import Design
-from elasticai.creator.vhdl.design_base.ports import Port
+from elasticai.creator.vhdl.design.design import Design
+from elasticai.creator.vhdl.design.ports import Port
 from elasticai.creator.vhdl.designs.rom import Rom
 from elasticai.creator.vhdl.savable import Path
 

elasticai/creator/nn/linear/layer.py

@@ -7,7 +7,7 @@
 from elasticai.creator.base_modules.two_complement_fixed_point_config import (
     FixedPointConfig,
 )
-from elasticai.creator.vhdl.design_base.design import Design
+from elasticai.creator.vhdl.design.design import Design
 from elasticai.creator.vhdl.translatable import Translatable
 
 from .design import FPLinear as FPLinearDesign

elasticai/creator/nn/precomputed/fp_precomputed_module.py

@@ -11,7 +11,7 @@
 from elasticai.creator.base_modules.two_complement_fixed_point_config import (
     FixedPointConfig,
 )
-from elasticai.creator.vhdl.design_base.design import Design
+from elasticai.creator.vhdl.design.design import Design
 from elasticai.creator.vhdl.designs.precomputed_scalar_function import (
     PrecomputedScalarFunction,
 )

elasticai/creator/nn/relu/design.py

@@ -3,7 +3,7 @@
     InProjectTemplate,
     module_to_package,
 )
-from elasticai.creator.vhdl.design_base.design import Design, Port
+from elasticai.creator.vhdl.design.design import Design, Port
 from elasticai.creator.vhdl.savable import Path
 
 

elasticai/creator/nn/relu/layer.py

@@ -1,5 +1,5 @@
 from elasticai.creator.base_modules.relu import ReLU
-from elasticai.creator.vhdl.design_base.design import Design
+from elasticai.creator.vhdl.design.design import Design
 from elasticai.creator.vhdl.translatable import Translatable
 
 from .design import FPReLU as FPReLUDesign

elasticai/creator/nn/sequential/design.py

@@ -15,8 +15,8 @@
     InProjectTemplate,
     module_to_package,
 )
-from elasticai.creator.vhdl.design_base.design import Design
-from elasticai.creator.vhdl.design_base.ports import Port
+from elasticai.creator.vhdl.design.design import Design
+from elasticai.creator.vhdl.design.ports import Port
 from elasticai.creator.vhdl.savable import Path
 
 

elasticai/creator/nn/sequential/layer.py

@@ -3,7 +3,7 @@
 
 import torch
 
-from elasticai.creator.vhdl.design_base.design import Design
+from elasticai.creator.vhdl.design.design import Design
 from elasticai.creator.vhdl.translatable import Translatable
 
 from .design import Sequential as _SequentialDesign

elasticai/creator/vhdl/auto_wire_protocols/port_definitions.py

@@ -4,8 +4,8 @@
 from elasticai.creator.vhdl.code_generation.vhdl_ports import (
     template_string_for_port_definition,
 )
-from elasticai.creator.vhdl.design_base import std_signals as _signals
-from elasticai.creator.vhdl.design_base.ports import Port
+from elasticai.creator.vhdl.design import std_signals as _signals
+from elasticai.creator.vhdl.design.ports import Port
 
 
 def create_port(

elasticai/creator/vhdl/base_template_generator/base_template_generator.py

@@ -8,8 +8,8 @@
 )
 
 """
-We want to programmatically use designs that are either hand-written or based on hand-written templates
-these designs need to adhere to a well defined protocol. As a hardware designer you specify your protocol
+We want to programmatically use shared_designs that are either hand-written or based on hand-written templates
+these shared_designs need to adhere to a well defined protocol. As a hardware designer you specify your protocol
 and the expected version of the elasticai.creator in a file called `design_meta.toml` that lives in the
 same folder as your `layer.py` that defines how the hdl code for the hardware design and the behaviour of
 the corresponding neural network layer in software.

elasticai/creator/vhdl/code_generation/code_abstractions.py

@@ -1,6 +1,6 @@
 from collections.abc import Sequence
 
-from elasticai.creator.vhdl.design_base.signal import Signal
+from elasticai.creator.vhdl.design.signal import Signal
 
 
 def _sorted_dict(items: dict[str, str]) -> dict[str, str]:

elasticai/creator/vhdl/code_generation/vhdl_ports.py

@@ -1,8 +1,8 @@
 from collections.abc import Callable, Sequence
 from itertools import chain
 
-from elasticai.creator.vhdl.design_base.ports import Port
-from elasticai.creator.vhdl.design_base.signal import Signal
+from elasticai.creator.vhdl.design.ports import Port
+from elasticai.creator.vhdl.design.signal import Signal
 
 
 def signal_string(name: str, direction: str, width: int | str) -> str:

elasticai/creator/vhdl/design_base/design.py → elasticai/creator/vhdl/design/design.py

@@ -1,6 +1,6 @@
 from abc import ABC, abstractmethod
 
-from elasticai.creator.vhdl.design_base.ports import Port
+from elasticai.creator.vhdl.design.ports import Port
 from elasticai.creator.vhdl.savable import Path, Savable
 
 

elasticai/creator/vhdl/design_base/ports.py → elasticai/creator/vhdl/design/ports.py

@@ -1,7 +1,7 @@
 from collections.abc import Iterator
 from itertools import chain
 
-from elasticai.creator.vhdl.design_base.signal import Signal
+from elasticai.creator.vhdl.design.signal import Signal
 
 
 class Port:

elasticai/creator/vhdl/design_base/std_signals.py → elasticai/creator/vhdl/design/std_signals.py

@@ -1,4 +1,4 @@
-from elasticai.creator.vhdl.design_base.signal import Signal
+from elasticai.creator.vhdl.design.signal import Signal
 
 
 def x(width: int) -> Signal:

elasticai/creator/vhdl/designs/precomputed_scalar_function/design.py → elasticai/creator/vhdl/shared_designs/precomputed_scalar_function/design.py

@@ -5,8 +5,8 @@
     InProjectTemplate,
     module_to_package,
 )
-from elasticai.creator.vhdl.design_base.design import Design
-from elasticai.creator.vhdl.design_base.ports import Port
+from elasticai.creator.vhdl.design.design import Design
+from elasticai.creator.vhdl.design.ports import Port
 from elasticai.creator.vhdl.savable import Path
 
 

elasticai/creator/vhdl/translatable.py

@@ -1,6 +1,6 @@
 from abc import ABC, abstractmethod
 
-from elasticai.creator.vhdl.design_base.design import Design
+from elasticai.creator.vhdl.design.design import Design
 
 
 class Translatable(ABC):

tests/nn/sequential/test_sequential_signal_widths_are_derived_from_subdesigns.py

@@ -2,8 +2,8 @@
 
 from elasticai.creator.nn.sequential.design import Sequential
 from elasticai.creator.vhdl.auto_wire_protocols.port_definitions import create_port
-from elasticai.creator.vhdl.design_base.design import Design
-from elasticai.creator.vhdl.design_base.ports import Port
+from elasticai.creator.vhdl.design.design import Design
+from elasticai.creator.vhdl.design.ports import Port
 from elasticai.creator.vhdl.savable import Path