feat: add basic vhdl parsing

elasticai/creator/hdl/vhdl/language.py

@@ -0,0 +1,28 @@
+from dataclasses import dataclass as _dataclass
+
+
+def _language_node(cls):
+    return _dataclass(eq=True, frozen=True)(cls)
+
+
+@_language_node
+class SignalDef:
+    name: str
+    direction: str
+    width: int
+
+
+@_language_node
+class Port:
+    signal_defs: list[SignalDef]
+
+
+@_language_node
+class Connection:
+    _to: str
+    _from: str
+
+
+@_language_node
+class Connections:
+    children: list[Connection]

elasticai/creator/hdl/vhdl/parser/parser.py

@@ -0,0 +1,38 @@
+from lark import Transformer
+
+from elasticai.creator.hdl.vhdl.language import Connection, Connections, Port, SignalDef
+
+from .standalone_parser import Lark_StandAlone
+
+
+class TreeToVHDL(Transformer):
+    def connection(self, s):
+        return Connection(_to=s[0].value, _from=s[1].value)
+
+    def connections(self, s):
+        return Connections(s)
+
+    def port(self, s):
+        return Port(s[0])
+
+    def vhdl(self, s):
+        return s[0]
+
+    def signal_defs(self, s):
+        return s
+
+    def signal_type(self, s):
+        v = s[0].data
+        if v.value == "std_logic":
+            return 0
+        else:
+            return int(s[1].value) - 1
+
+    def signal_def(self, s):
+        name, direction, width = s
+        name = name.value
+        direction = direction.data
+        return SignalDef(name=name, direction=direction, width=width)
+
+
+parser = Lark_StandAlone(transformer=TreeToVHDL())

elasticai/creator/hdl/vhdl/parser/vhdl_grammar.lark

@@ -0,0 +1,20 @@
+vhdl : port | connections
+connections: connection+
+port : "port" "(" signal_defs ")" ";"
+signal_defs : signal_def | signal_def+ ";" signal_def
+signal_def : ID ":" direction signal_type
+direction: "in" -> in
+  | "out" -> out
+signal_type: std_logic
+ | std_logic_vector "(" NUMBER "-" "1" "downto" "0" ")"
+std_logic_vector: "std_logic_vector"
+std_logic: "std_logic"
+connection: ID "<" "=" ID ";"
+
+ID: /[a-zA-Z_][a-zA-Z0-9_]*/
+NUMBER: /[0-9]+/
+COMMENT: /--.*$/
+WHITESPACE: /\s+/
+
+%ignore WHITESPACE
+%ignore COMMENT

pyproject.toml

@@ -36,6 +36,7 @@ setuptools = "^67.5.1"
 
 [tool.poetry.group.dev.dependencies]
 pytest-bdd = "^6.1.1"
+lark = "^1.1.5"
 
 [tool.pylint]
 max-line-length = 88

tests/vhdl/test_parser.py

@@ -0,0 +1,25 @@
+from elasticai.creator.hdl.vhdl.language import Connection, Connections, Port, SignalDef
+from elasticai.creator.hdl.vhdl.parser.parser import parser
+
+
+def test_parsing_connections():
+    expected = Connections(
+        [Connection(_from="y", _to="x"), Connection(_from="b", _to="a")]
+    )
+    code = "x <= y; a <= b;"
+    actual = parser.parse(code)
+    assert actual == expected
+
+
+def test_parsing_port():
+    v = parser.parse(
+        "port ( my_signal : in std_logic; my_other : out std_logic_vector(5 - 1 downto"
+        " 0));"
+    )
+
+    assert v == Port(
+        [
+            SignalDef(n, d, w)
+            for n, d, w in (("my_signal", "in", 0), ("my_other", "out", 4))
+        ]
+    )