fix: use elsif in lookup table

es-ude · Jun 9, 2023 · f375ba3 · f375ba3
1 parent c0756b3
commit f375ba3
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Showing 2 changed files with 14 additions and 9 deletions.
diff --git a/...esigns/monotonously_increasing_precomputed_scalar_function/precomputed_scalar_function.py b/...esigns/monotonously_increasing_precomputed_scalar_function/precomputed_scalar_function.py
@@ -49,10 +49,15 @@ def save_to(self, destination: Path) -> None:
         process_content = []
 
         pairs = list(self._compute_io_pairs().items())
-        for input, output in pairs[:-1]:
+        input_value, output_value = pairs[0]
+        process_content.append(
+            f"if signed_x <= {input_value} then "
+            f"signed_y <= to_signed({output_value}, {self._width});"
+        )
+        for input_value, output_value in pairs[1:-1]:
             process_content.append(
-                f"if signed_x <= {input} then signed_y <= to_signed({output},"
-                f" {self._width});"
+                f"elsif signed_x <= {input_value} then "
+                f"signed_y <= to_signed({output_value}, {self._width});"
             )
         _, output = pairs[-1]
         process_content.append(f"else signed_y <= to_signed({output}, {self._width});")

diff --git a/tests/vhdl/designs/test_fp_monotonously_increasing_module.py b/tests/vhdl/designs/test_fp_monotonously_increasing_module.py
@@ -30,9 +30,9 @@ def test_vhdl_code_matches_expected_for_tanh_as_base_module() -> None:
     tanh_process : process(x)
     begin
         if signed_x <= 20 then signed_y <= to_signed(3, 8);
-        if signed_x <= 10 then signed_y <= to_signed(3, 8);
-        if signed_x <= 0 then signed_y <= to_signed(0, 8);
-        if signed_x <= -10 then signed_y <= to_signed(-3, 8);
+        elsif signed_x <= 10 then signed_y <= to_signed(3, 8);
+        elsif signed_x <= 0 then signed_y <= to_signed(0, 8);
+        elsif signed_x <= -10 then signed_y <= to_signed(-3, 8);
         else signed_y <= to_signed(-3, 8);
         end if;
     end process;
@@ -74,9 +74,9 @@ def test_vhdl_code_matches_expected_for_sigmoid_as_base_module() -> None:
     sigmoid_process : process(x)
     begin
         if signed_x <= 20 then signed_y <= to_signed(3, 8);
-        if signed_x <= 10 then signed_y <= to_signed(3, 8);
-        if signed_x <= 0 then signed_y <= to_signed(2, 8);
-        if signed_x <= -10 then signed_y <= to_signed(0, 8);
+        elsif signed_x <= 10 then signed_y <= to_signed(3, 8);
+        elsif signed_x <= 0 then signed_y <= to_signed(2, 8);
+        elsif signed_x <= -10 then signed_y <= to_signed(0, 8);
         else signed_y <= to_signed(0, 8);
         end if;
     end process;