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Rework DMA descriptors
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bugadani committed Dec 29, 2023
1 parent 2e2d67f commit 165820f
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Showing 9 changed files with 206 additions and 306 deletions.
3 changes: 3 additions & 0 deletions CHANGELOG.md
Original file line number Diff line number Diff line change
Expand Up @@ -13,9 +13,12 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0

- ESP32-C6: Properly initialize PMU (#974)
- Implement overriding base mac address (#1044)
- DmaDescriptor struct to better model the hardware (#1054)

### Changed

- DMA descriptor count no longer needs to be multiplied by 3 (#1054)

### Fixed

- ESP32: correct gpio 32/33 in errata36() (#1053)
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55 changes: 6 additions & 49 deletions esp-hal-common/src/dma/gdma.rs
Original file line number Diff line number Diff line change
Expand Up @@ -30,16 +30,6 @@ use crate::{
system::{Peripheral, PeripheralClockControl},
};

#[cold]
fn on_tx_descriptor_not_divisible_by_3() {
panic!("The number of tx descriptors must be a multiple of 3");
}

#[cold]
fn on_rx_descriptor_not_divisible_by_3() {
panic!("The number of rx descriptors must be a multiple of 3");
}

macro_rules! impl_channel {
($num: literal) => {
paste::paste! {
Expand Down Expand Up @@ -562,57 +552,24 @@ macro_rules! impl_channel {
impl [<ChannelCreator $num>] {
/// Configure the channel for use
///
/// Descriptors should be sized as `((CHUNK_SIZE + 4091) / 4092) * 3`. I.e., to
/// transfer buffers of size `1..=4092`, you need 3 descriptors. The number of
/// descriptors must be a multiple of 3.
/// Descriptors should be sized as `(CHUNK_SIZE + 4091) / 4092`. I.e., to
/// transfer buffers of size `1..=4092`, you need 1 descriptor.
pub fn configure<'a>(
self,
burst_mode: bool,
tx_descriptors: &'a mut [u32],
rx_descriptors: &'a mut [u32],
tx_descriptors: &'a mut [DmaDescriptor],
rx_descriptors: &'a mut [DmaDescriptor],
priority: DmaPriority,
) -> Channel<'a, [<Channel $num>]> {
if tx_descriptors.len() % 3 != 0 {
on_tx_descriptor_not_divisible_by_3();
}

if rx_descriptors.len() % 3 != 0 {
on_rx_descriptor_not_divisible_by_3();
}

let mut tx_impl = [<Channel $num TxImpl>] {};
tx_impl.init(burst_mode, priority);

let tx_channel = ChannelTx {
descriptors: tx_descriptors,
burst_mode,
tx_impl: tx_impl,
write_offset: 0,
write_descr_ptr: core::ptr::null(),
available: 0,
last_seen_handled_descriptor_ptr: core::ptr::null(),
buffer_start: core::ptr::null(),
buffer_len: 0,
_phantom: PhantomData::default(),
};

let mut rx_impl = [<Channel $num RxImpl>] {};
rx_impl.init(burst_mode, priority);

let rx_channel = ChannelRx {
descriptors: rx_descriptors,
burst_mode,
rx_impl: rx_impl,
read_descr_ptr: core::ptr::null(),
available: 0,
last_seen_handled_descriptor_ptr: core::ptr::null(),
read_buffer_start: core::ptr::null(),
_phantom: PhantomData::default(),
};

Channel {
tx: tx_channel,
rx: rx_channel,
tx: ChannelTx::new(tx_descriptors, tx_impl, burst_mode),
rx: ChannelRx::new(rx_descriptors, rx_impl, burst_mode),
}
}
}
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