Rename dma_ functions

esp-hal/CHANGELOG.md

@@ -21,6 +21,7 @@ and this project adheres to [Semantic Versioning](https://semver.org/spec/v2.0.0
 
 - Peripheral type erasure for SPI (#2334)
 - The SPI driver has been rewritten to allow using half-duplex and full-duplex functionality on the same bus. See the migration guide for details. (#2373)
+- Renamed `SpiDma` functions: `dma_transfer` to `transfer`, `dma_write` to `write`, `dma_read` to `read`. (#2373)
 
 ### Fixed
 

esp-hal/src/spi/master.rs

@@ -1234,7 +1234,7 @@ mod dma {
         /// bytes.
         #[allow(clippy::type_complexity)]
         #[cfg_attr(place_spi_driver_in_ram, ram)]
-        pub fn dma_write<TX: DmaTxBuffer>(
+        pub fn write<TX: DmaTxBuffer>(
             mut self,
             mut buffer: TX,
         ) -> Result<SpiDmaTransfer<'d, M, TX, T>, (Error, Self, TX)> {
@@ -1273,7 +1273,7 @@ mod dma {
         /// received is 32736 bytes.
         #[allow(clippy::type_complexity)]
         #[cfg_attr(place_spi_driver_in_ram, ram)]
-        pub fn dma_read<RX: DmaRxBuffer>(
+        pub fn read<RX: DmaRxBuffer>(
             mut self,
             mut buffer: RX,
         ) -> Result<SpiDmaTransfer<'d, M, RX, T>, (Error, Self, RX)> {
@@ -1311,7 +1311,7 @@ mod dma {
         /// sent/received is 32736 bytes.
         #[allow(clippy::type_complexity)]
         #[cfg_attr(place_spi_driver_in_ram, ram)]
-        pub fn dma_transfer<RX: DmaRxBuffer, TX: DmaTxBuffer>(
+        pub fn transfer<RX: DmaRxBuffer, TX: DmaTxBuffer>(
             mut self,
             mut rx_buffer: RX,
             mut tx_buffer: TX,

esp-hal/src/spi/slave.rs

@@ -48,7 +48,7 @@
 //! let mut send = tx_buffer;
 //!
 //! let transfer = spi
-//!     .dma_transfer(&mut receive, &mut send)
+//!     .transfer(&mut receive, &mut send)
 //!     .unwrap();
 //!
 //! transfer.wait().unwrap();
@@ -313,7 +313,7 @@ pub mod dma {
         /// sent is 32736 bytes.
         ///
         /// The write is driven by the SPI master's sclk signal and cs line.
-        pub fn dma_write<'t, TXBUF>(
+        pub fn write<'t, TXBUF>(
             &'t mut self,
             words: &'t TXBUF,
         ) -> Result<DmaTransferTx<'t, Self>, Error>
@@ -348,7 +348,7 @@ pub mod dma {
         /// received is 32736 bytes.
         ///
         /// The read is driven by the SPI master's sclk signal and cs line.
-        pub fn dma_read<'t, RXBUF>(
+        pub fn read<'t, RXBUF>(
             &'t mut self,
             words: &'t mut RXBUF,
         ) -> Result<DmaTransferRx<'t, Self>, Error>
@@ -384,7 +384,7 @@ pub mod dma {
         ///
         /// The data transfer is driven by the SPI master's sclk signal and cs
         /// line.
-        pub fn dma_transfer<'t, RXBUF, TXBUF>(
+        pub fn transfer<'t, RXBUF, TXBUF>(
             &'t mut self,
             read_buffer: &'t mut RXBUF,
             words: &'t TXBUF,

examples/src/bin/spi_loopback_dma.rs

@@ -74,7 +74,7 @@ fn main() -> ! {
         i = i.wrapping_add(1);
 
         let transfer = spi
-            .dma_transfer(dma_rx_buf, dma_tx_buf)
+            .transfer(dma_rx_buf, dma_tx_buf)
             .map_err(|e| e.0)
             .unwrap();
         // here we could do something else while DMA transfer is in progress

examples/src/bin/spi_loopback_dma_psram.rs

@@ -111,7 +111,7 @@ fn main() -> ! {
         i = i.wrapping_add(1);
 
         let transfer = spi
-            .dma_transfer(dma_rx_buf, dma_tx_buf)
+            .transfer(dma_rx_buf, dma_tx_buf)
             .map_err(|e| e.0)
             .unwrap();
 

examples/src/bin/spi_slave_dma.rs

@@ -107,11 +107,9 @@ fn main() -> ! {
 
         println!("Iteration {i}");
 
-        println!("Do `dma_transfer`");
+        println!("Do `transfer`");
 
-        let transfer = spi
-            .dma_transfer(&mut slave_receive, &mut slave_send)
-            .unwrap();
+        let transfer = spi.transfer(&mut slave_receive, &mut slave_send).unwrap();
 
         bitbang_master(
             master_send,
@@ -133,9 +131,9 @@ fn main() -> ! {
 
         delay.delay_millis(250);
 
-        println!("Do `dma_read`");
+        println!("Do `read`");
         slave_receive.fill(0xff);
-        let transfer = spi.dma_read(&mut slave_receive).unwrap();
+        let transfer = spi.read(&mut slave_receive).unwrap();
 
         bitbang_master(
             master_send,
@@ -155,8 +153,8 @@ fn main() -> ! {
 
         delay.delay_millis(250);
 
-        println!("Do `dma_write`");
-        let transfer = spi.dma_write(&mut slave_send).unwrap();
+        println!("Do `write`");
+        let transfer = spi.write(&mut slave_send).unwrap();
 
         master_receive.fill(0);
 

hil-test/tests/spi_full_duplex.rs

@@ -211,11 +211,11 @@ mod tests {
 
         for i in 1..4 {
             dma_rx_buf.as_mut_slice().copy_from_slice(&[5, 5, 5, 5, 5]);
-            let transfer = spi.dma_read(dma_rx_buf).map_err(|e| e.0).unwrap();
+            let transfer = spi.read(dma_rx_buf).map_err(|e| e.0).unwrap();
             (spi, dma_rx_buf) = transfer.wait();
             assert_eq!(dma_rx_buf.as_slice(), &[0, 0, 0, 0, 0]);
 
-            let transfer = spi.dma_write(dma_tx_buf).map_err(|e| e.0).unwrap();
+            let transfer = spi.write(dma_tx_buf).map_err(|e| e.0).unwrap();
             (spi, dma_tx_buf) = transfer.wait();
             assert_eq!(unit.get_value(), (i * 3 * DMA_BUFFER_SIZE) as _);
         }
@@ -244,12 +244,12 @@ mod tests {
 
         for i in 1..4 {
             dma_rx_buf.as_mut_slice().copy_from_slice(&[5, 5, 5, 5, 5]);
-            let transfer = spi.dma_read(dma_rx_buf).map_err(|e| e.0).unwrap();
+            let transfer = spi.read(dma_rx_buf).map_err(|e| e.0).unwrap();
             (spi, dma_rx_buf) = transfer.wait();
             assert_eq!(dma_rx_buf.as_slice(), &[0, 0, 0, 0, 0]);
 
             let transfer = spi
-                .dma_transfer(dma_rx_buf, dma_tx_buf)
+                .transfer(dma_rx_buf, dma_tx_buf)
                 .map_err(|e| e.0)
                 .unwrap();
             (spi, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
@@ -276,7 +276,7 @@ mod tests {
             dma_tx_buf.as_mut_slice()[0] = i as u8;
             *dma_tx_buf.as_mut_slice().last_mut().unwrap() = i as u8;
             let transfer = spi
-                .dma_transfer(dma_rx_buf, dma_tx_buf)
+                .transfer(dma_rx_buf, dma_tx_buf)
                 .map_err(|e| e.0)
                 .unwrap();
 
@@ -302,7 +302,7 @@ mod tests {
             .spi
             .with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
         let transfer = spi
-            .dma_transfer(dma_rx_buf, dma_tx_buf)
+            .transfer(dma_rx_buf, dma_tx_buf)
             .map_err(|e| e.0)
             .unwrap();
         let (spi, (dma_rx_buf, mut dma_tx_buf)) = transfer.wait();
@@ -313,7 +313,7 @@ mod tests {
         dma_tx_buf.fill(&[0xaa, 0xdd, 0xef, 0xbe]);
 
         let transfer = spi
-            .dma_transfer(dma_rx_buf, dma_tx_buf)
+            .transfer(dma_rx_buf, dma_tx_buf)
             .map_err(|e| e.0)
             .unwrap();
         let (_, (dma_rx_buf, dma_tx_buf)) = transfer.wait();
@@ -471,18 +471,18 @@ mod tests {
 
         dma_tx_buf.fill(&[0xde, 0xad, 0xbe, 0xef]);
 
-        let transfer = spi.dma_write(dma_tx_buf).map_err(|e| e.0).unwrap();
+        let transfer = spi.write(dma_tx_buf).map_err(|e| e.0).unwrap();
         let (spi, dma_tx_buf) = transfer.wait();
 
         dma_rx_buf.as_mut_slice().fill(0);
-        let transfer = spi.dma_read(dma_rx_buf).map_err(|e| e.0).unwrap();
+        let transfer = spi.read(dma_rx_buf).map_err(|e| e.0).unwrap();
         let (spi, mut dma_rx_buf) = transfer.wait();
 
-        let transfer = spi.dma_write(dma_tx_buf).map_err(|e| e.0).unwrap();
+        let transfer = spi.write(dma_tx_buf).map_err(|e| e.0).unwrap();
         let (spi, _dma_tx_buf) = transfer.wait();
 
         dma_rx_buf.as_mut_slice().fill(0);
-        let transfer = spi.dma_read(dma_rx_buf).map_err(|e| e.0).unwrap();
+        let transfer = spi.read(dma_rx_buf).map_err(|e| e.0).unwrap();
         let (_, dma_rx_buf) = transfer.wait();
 
         assert_eq!(&[0xff, 0xff, 0xff, 0xff], dma_rx_buf.as_slice());
@@ -505,7 +505,7 @@ mod tests {
             .with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
 
         let mut transfer = spi
-            .dma_transfer(dma_rx_buf, dma_tx_buf)
+            .transfer(dma_rx_buf, dma_tx_buf)
             .map_err(|e| e.0)
             .unwrap();
 
@@ -528,7 +528,7 @@ mod tests {
             .with_dma(ctx.dma_channel.configure(false, DmaPriority::Priority0));
 
         let mut transfer = spi
-            .dma_transfer(dma_rx_buf, dma_tx_buf)
+            .transfer(dma_rx_buf, dma_tx_buf)
             .map_err(|e| e.0)
             .unwrap();
 
@@ -538,7 +538,7 @@ mod tests {
         spi.change_bus_frequency(10000.kHz());
 
         let transfer = spi
-            .dma_transfer(dma_rx_buf, dma_tx_buf)
+            .transfer(dma_rx_buf, dma_tx_buf)
             .map_err(|e| e.0)
             .unwrap();
 
@@ -563,7 +563,7 @@ mod tests {
         );
 
         let mut transfer = spi
-            .dma_transfer(dma_rx_buf, dma_tx_buf)
+            .transfer(dma_rx_buf, dma_tx_buf)
             .map_err(|e| e.0)
             .unwrap();
 

hil-test/tests/spi_slave.rs

@@ -170,7 +170,7 @@ mod tests {
         }
         slave_receive.fill(0xFF);
 
-        let transfer = spi.dma_transfer(slave_receive, &slave_send).unwrap();
+        let transfer = spi.transfer(slave_receive, &slave_send).unwrap();
 
         ctx.bitbang_spi.transfer_buf(master_receive, master_send);