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Add support for the ESP32-C6 #392

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merged 64 commits into from
Feb 27, 2023
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a571bf6
Create the `esp32c6-hal` package
jessebraham Jan 5, 2023
a2c6145
Teach `esp-hal-common` about the ESP32-C6
jessebraham Jan 6, 2023
f358cad
Get a number of peripheral drivers building for the ESP32-C6
jessebraham Jan 6, 2023
fc65b3f
Create the `esp32c6-hal` package
jessebraham Jan 5, 2023
bea1242
Simplify and fix the linker script
bjoernQ Jan 20, 2023
5f8e2d1
C6: add I2S
JurajSadel Jan 25, 2023
6db490d
Create the `esp32c6-hal` package
jessebraham Jan 5, 2023
a38ced1
Teach `esp-hal-common` about the ESP32-C6
jessebraham Jan 6, 2023
730f57f
Get a number of peripheral drivers building for the ESP32-C6
jessebraham Jan 6, 2023
3cec8bb
Create the `esp32c6-hal` package
jessebraham Jan 5, 2023
1e5ef3c
C6: update
JurajSadel Jan 20, 2023
e6df68d
Simplify and fix the linker script
bjoernQ Jan 20, 2023
d2b0734
update
JurajSadel Jan 24, 2023
bde4bb5
C6: add I2S
JurajSadel Jan 25, 2023
6351eee
update
JurajSadel Jan 24, 2023
51cb4c0
C6 Interrupts
bjoernQ Jan 25, 2023
753414a
C6: Update build.rs, linker scripts and initial examples
JurajSadel Jan 27, 2023
dece8b4
C6: RMT
JurajSadel Jan 27, 2023
3ad20aa
Fix interrupt handling
bjoernQ Jan 26, 2023
731f1cb
Fix `ClockControl::configure`
bjoernQ Jan 27, 2023
b0e7a59
C6: revert to I2S0 instead of just I2S
JurajSadel Jan 30, 2023
ae4e4b5
C6: rebase and update
JurajSadel Feb 1, 2023
a4edc46
RTC not buildable
JurajSadel Feb 2, 2023
988b1d0
Implement RWDT and SWD disable
bjoernQ Feb 2, 2023
ac4c447
C6: working LEDC
JurajSadel Feb 3, 2023
8ddaf7e
C6: working RMT
JurajSadel Feb 3, 2023
2b7fd7d
C6: add aes
JurajSadel Feb 7, 2023
b100cb2
C6: add mcpwm
JurajSadel Feb 7, 2023
9968157
C6: add rtc_cntln - not finished
JurajSadel Feb 7, 2023
cfb8445
C6: update and formatting
JurajSadel Feb 7, 2023
f9b7e19
C6: add pcnt
JurajSadel Feb 7, 2023
a7e14a9
C6: add examples and format
JurajSadel Feb 7, 2023
b7f0316
Remove inline assembly, fix interrupts and linker scripts
jessebraham Feb 7, 2023
a2e4c93
Remove unused features, update cargo config for atomic emu, misc cleanup
jessebraham Feb 7, 2023
8217147
Get ADC building and example "working" (as much as it ever does)
jessebraham Feb 7, 2023
a933093
Remove a bunch of unused constants which were copied from ESP-IDF
jessebraham Feb 7, 2023
93f926f
The `mcpwm` example now works correctly
jessebraham Feb 7, 2023
59a599d
Get `TWAI` peripheral driver building for C6
jessebraham Feb 8, 2023
46487eb
Clean up the `rtc_cntl` module and get all the other HALs building again
jessebraham Feb 8, 2023
4f97342
Add the C6 to our CI workflow
jessebraham Feb 8, 2023
403c640
Fix various things that have been missed when rebasing
jessebraham Feb 8, 2023
08f6f19
C6: Small updates in wdt (#1)
JurajSadel Feb 9, 2023
730b6b3
Update `esp-println` dependency to fix build errors
jessebraham Feb 9, 2023
e903e90
Fix formatting issues causing pre-commit hook to fail
jessebraham Feb 9, 2023
3622bc1
Get some more examples working
jessebraham Feb 9, 2023
9747426
Working `ram` example
jessebraham Feb 10, 2023
e41ecdd
Sync with changes in `main` after rebasing
jessebraham Feb 10, 2023
28ece39
Working `embassy_spi` example
jessebraham Feb 10, 2023
dd7f469
Use a git dependency for the PAC until we publish a release
jessebraham Feb 10, 2023
7dd27e5
Fix I2S for ESP32-C6
bjoernQ Feb 14, 2023
39444ba
Fix esp32c6 direct boot (#4)
MabezDev Feb 22, 2023
d16cab7
Update RWDT and refactor RTC (#3)
JurajSadel Feb 23, 2023
87cf485
Make required changes to include new `RADIO` peripheral
jessebraham Feb 23, 2023
0d3fd81
Use published versions of PAC and `esp-println`
jessebraham Feb 23, 2023
a381487
Use the correct target extensions (`imac`)
jessebraham Feb 24, 2023
572e99d
Fix the super watchdog timer, plus a few more examples
jessebraham Feb 24, 2023
dc309ea
Fix UART clock configuration
jessebraham Feb 24, 2023
716163b
Make sure to sync UART registers when configuring AT cmd detection
bjoernQ Feb 27, 2023
2f5972b
Disable APM in direct-boot mode
bjoernQ Feb 27, 2023
3eb273a
Address a number of review comments
jessebraham Feb 27, 2023
6641a0d
Fix `SPI` clocks and `rtc_watchdog` example (#6)
JurajSadel Feb 27, 2023
9e5f298
README and example fixes/cleanup
jessebraham Feb 27, 2023
ed59cd9
Add I2C peripheral enable and reset
bjoernQ Feb 27, 2023
e678120
Fix `ApbSarAdc` configuration in `system.rs`
jessebraham Feb 27, 2023
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C6: RMT
  • Loading branch information
JurajSadel authored and jessebraham committed Feb 23, 2023
commit dece8b4be5bf964f5a2921a8d3c6d874e99d5eb0
8 changes: 4 additions & 4 deletions esp-hal-common/src/gpio/esp32c6.rs
Original file line number Diff line number Diff line change
@@ -85,8 +85,8 @@ pub enum InputSignal {
FSPICS0 = 68,
PARL_RX_CLK = 69,
PARL_TX_CLK = 70,
RMT_SIG_IN0 = 71,
MODEM_DIAG1 = 72,
RMT_SIG_0 = 71,
RMT_SIG_1 = 72,
TWAI0_RX = 73,
TWAI1_RX = 77,
PWM0_SYNC0 = 87,
@@ -186,8 +186,8 @@ pub enum OutputSignal {
FSPICS0 = 68,
SDIO_TOHOST_INT = 69,
PARL_TX_CLK = 70,
RMT_SIG_OUT0 = 71,
RMT_SIG_OUT1 = 72,
RMT_SIG_0 = 71,
RMT_SIG_1 = 72,
TWAI0_TX = 73,
TWAI0_BUS_OFF_ON = 74,
TWAI0_CLKOUT = 75,
12 changes: 6 additions & 6 deletions esp-hal-common/src/lib.rs
Original file line number Diff line number Diff line change
@@ -56,8 +56,8 @@ pub mod trapframe {
pub use xtensa_lx_rt::exception::Context as TrapFrame;
}

// #[cfg(rmt)]
// pub use self::pulse_control::PulseControl;
#[cfg(rmt)]
pub use self::pulse_control::PulseControl;
// #[cfg(usb_serial_jtag)]
// pub use self::usb_serial_jtag::UsbSerialJtag;
// pub use self::{
@@ -91,8 +91,8 @@ pub mod otg_fs;
pub mod pcnt;
pub mod peripheral;
pub mod prelude;
// #[cfg(rmt)]
// pub mod pulse_control;
#[cfg(rmt)]
pub mod pulse_control;
#[cfg(radio)]
pub mod radio;
pub mod rng;
@@ -108,8 +108,8 @@ pub mod timer;
pub mod uart;
#[cfg(usb_serial_jtag)]
pub mod usb_serial_jtag;
// #[cfg(rmt)]
// pub mod utils;
#[cfg(rmt)]
pub mod utils;

#[cfg_attr(esp32, path = "cpu_control/esp32.rs")]
#[cfg_attr(esp32s3, path = "cpu_control/esp32s3.rs")]
46 changes: 23 additions & 23 deletions esp-hal-common/src/prelude.rs
Original file line number Diff line number Diff line change
@@ -20,45 +20,45 @@ pub use fugit::{
};
pub use nb;

#[cfg(any(esp32c2, esp32c3))]
pub use crate::analog::SarAdcExt as _esp_hal_analog_SarAdcExt;
#[cfg(any(esp32, esp32s2, esp32s3))]
pub use crate::analog::SensExt as _esp_hal_analog_SensExt;
//#[cfg(rmt)]
//pub use crate::pulse_control::{
// ConfiguredChannel as _esp_hal_pulse_control_ConfiguredChannel,
// OutputChannel as _esp_hal_pulse_control_OutputChannel,
//};
// #[cfg(any(esp32c2, esp32c3))]
// pub use crate::analog::SarAdcExt as _esp_hal_analog_SarAdcExt;
// #[cfg(any(esp32, esp32s2, esp32s3))]
// pub use crate::analog::SensExt as _esp_hal_analog_SensExt;
// #[cfg(rmt)]
// pub use crate::pulse_control::{
// ConfiguredChannel as _esp_hal_pulse_control_ConfiguredChannel,
// OutputChannel as _esp_hal_pulse_control_OutputChannel,
// };
#[cfg(radio)]
pub use crate::radio::RadioExt as _esp_hal_RadioExt;
#[cfg(any(esp32, esp32s2))]
pub use crate::spi::dma::WithDmaSpi3 as _esp_hal_spi_dma_WithDmaSpi3;
pub use crate::{
clock::Clock as _esp_hal_clock_Clock,
dma::{
DmaTransfer as _esp_hal_dma_DmaTransfer,
DmaTransferRxTx as _esp_hal_dma_DmaTransferRxTx,
DmaTransfer as _esp_hal_dma_DmaTransfer,
DmaTransferRxTx as _esp_hal_dma_DmaTransferRxTx,
},
entry,
gpio::{
InputPin as _esp_hal_gpio_InputPin,
OutputPin as _esp_hal_gpio_OutputPin,
Pin as _esp_hal_gpio_Pin,
},
// i2c::Instance as _esp_hal_i2c_Instance,
// ledc::{
// channel::{
// ChannelHW as _esp_hal_ledc_channel_ChannelHW,
// ChannelIFace as _esp_hal_ledc_channel_ChannelIFace,
// },
// timer::{
// TimerHW as _esp_hal_ledc_timer_TimerHW,
// TimerIFace as _esp_hal_ledc_timer_TimerIFace,
// },
// },
i2c::Instance as _esp_hal_i2c_Instance,
ledc::{
channel::{
ChannelHW as _esp_hal_ledc_channel_ChannelHW,
ChannelIFace as _esp_hal_ledc_channel_ChannelIFace,
},
timer::{
TimerHW as _esp_hal_ledc_timer_TimerHW,
TimerIFace as _esp_hal_ledc_timer_TimerIFace,
},
},
macros::*,
spi::{
dma::WithDmaSpi2 as _esp_hal_spi_dma_WithDmaSpi2,
dma::WithDmaSpi2 as _esp_hal_spi_dma_WithDmaSpi2,
Instance as _esp_hal_spi_Instance,
InstanceDma as _esp_hal_spi_InstanceDma,
},
41 changes: 23 additions & 18 deletions esp-hal-common/src/pulse_control.rs
Original file line number Diff line number Diff line change
@@ -21,6 +21,9 @@
//! * The **ESP32-C3** has 4 channels, `Channel0` and `Channel1` hardcoded for
//! transmitting signals and `Channel2` and `Channel3` hardcoded for receiving
//! signals.
//! * The **ESP32-C6** has 4 channels, `Channel0` and `Channel1` hardcoded for
//! transmitting signals and `Channel2` and `Channel3` hardcoded for receiving
//! signals.
//! * The **ESP32-S2** has 4 channels, each of them can be either receiver or
//! transmitter.
//! * The **ESP32-S3** has 8 channels, `Channel0`-`Channel3` hardcdoded for
@@ -124,7 +127,7 @@ pub enum RepeatMode {
}

/// Specify the clock source for the RMT peripheral
#[cfg(any(esp32c3, esp32s3))]
#[cfg(any(esp32c3, esp32c6, esp32s3))]
#[derive(Debug, Copy, Clone)]
pub enum ClockSource {
/// Application-level clock
@@ -150,14 +153,16 @@ pub enum ClockSource {
// to the RMT channel
#[cfg(any(esp32s2, esp32))]
const CHANNEL_RAM_SIZE: u8 = 64;
#[cfg(any(esp32c3, esp32s3))]
#[cfg(any(esp32c3, esp32c6, esp32s3))]
const CHANNEL_RAM_SIZE: u8 = 48;

// Specifies where the RMT RAM section starts for the particular ESP32 variant
#[cfg(esp32s2)]
const RMT_RAM_START: usize = 0x3f416400;
#[cfg(esp32c3)]
const RMT_RAM_START: usize = 0x60016400;
#[cfg(esp32c6)]
const RMT_RAM_START: usize = 0x60006400;
#[cfg(esp32)]
const RMT_RAM_START: usize = 0x3ff56800;
#[cfg(esp32s3)]
@@ -283,7 +288,7 @@ macro_rules! channel_instance {
let mut channel = $cxi { mem_offset: 0 };

cfg_if::cfg_if! {
if #[cfg(any(esp32c3, esp32s3))] {
if #[cfg(any(esp32c3, esp32c6, esp32s3))] {
// Apply default configuration
unsafe { &*RMT::PTR }.ch_tx_conf0[$num].modify(|_, w| unsafe {
// Configure memory block size
@@ -459,7 +464,7 @@ macro_rules! channel_instance {
}
}

#[cfg(any(esp32c3, esp32s3))]
#[cfg(any(esp32c3, esp32c6, esp32s3))]
conf_reg.modify(|_, w| {
// Set config update bit
w.conf_update().set_bit()
@@ -540,14 +545,14 @@ macro_rules! channel_instance {
}

// always enable tx wrap
#[cfg(any(esp32c3, esp32s3))]
#[cfg(any(esp32c3, esp32c6, esp32s3))]
unsafe { &*RMT::PTR }.ch_tx_conf0[$num].modify(|_, w| {
w.mem_tx_wrap_en()
.set_bit()
});

// apply configuration updates
#[cfg(any(esp32c3, esp32s3))]
#[cfg(any(esp32c3, esp32c6, esp32s3))]
unsafe { &*RMT::PTR }.ch_tx_conf0[$num].modify(|_, w| {
w.conf_update()
.set_bit()
@@ -577,9 +582,9 @@ macro_rules! channel_instance {
#[cfg(esp32)]
false,
// The C3/S3 have a slightly different interrupt naming scheme
#[cfg(any(esp32, feature= "esp32s2"))]
#[cfg(any(esp32, esp32s2))]
unsafe { interrupts.ch_err_int_raw($num).bit() },
#[cfg(any(esp32c3, feature= "esp32s3"))]
#[cfg(any(esp32c3, esp32c6, esp32s3))]
unsafe { interrupts.ch_tx_err_int_raw($num).bit() },
unsafe { interrupts.ch_tx_thr_event_int_raw($num).bit() },
) {
@@ -612,9 +617,9 @@ macro_rules! channel_instance {
#[cfg(esp32)]
false,
// The C3/S3 have a slightly different interrupt naming scheme
#[cfg(any(esp32, feature= "esp32s2"))]
#[cfg(any(esp32, esp32s2))]
unsafe { interrupts.ch_err_int_raw($num).bit() },
#[cfg(any(esp32c3, feature= "esp32s3"))]
#[cfg(any(esp32c3, esp32c6, esp32s3))]
unsafe { interrupts.ch_tx_err_int_raw($num).bit() },
unsafe { interrupts.ch_tx_thr_event_int_raw($num).bit() },
))
@@ -632,7 +637,7 @@ macro_rules! channel_instance {
/// previously a sequence was sent with `RepeatMode::Forever`.
fn stop_transmission(&self) {
cfg_if::cfg_if! {
if #[cfg(any(esp32c3, esp32s3))] {
if #[cfg(any(esp32c3, esp32c6, esp32s3))] {
unsafe { &*RMT::PTR }
.ch_tx_conf0[$num]
.modify(|_, w| w.tx_stop().set_bit());
@@ -666,7 +671,7 @@ macro_rules! output_channel {
#[inline(always)]
fn set_idle_output_level(&mut self, level: bool) -> &mut Self {
cfg_if::cfg_if! {
if #[cfg(any(esp32c3, esp32s3))] {
if #[cfg(any(esp32c3, esp32c6, esp32s3))] {
unsafe { &*RMT::PTR }
.ch_tx_conf0[$num]
.modify(|_, w| w.idle_out_lv().bit(level));
@@ -683,7 +688,7 @@ macro_rules! output_channel {
#[inline(always)]
fn set_idle_output(&mut self, state: bool) -> &mut Self {
cfg_if::cfg_if! {
if #[cfg(any(esp32c3, esp32s3))] {
if #[cfg(any(esp32c3, esp32c6, esp32s3))] {
unsafe { &*RMT::PTR }
.ch_tx_conf0[$num]
.modify(|_, w| w.idle_out_en().bit(state));
@@ -700,7 +705,7 @@ macro_rules! output_channel {
#[inline(always)]
fn set_channel_divider(&mut self, divider: u8) -> &mut Self {
cfg_if::cfg_if! {
if #[cfg(any(esp32c3, esp32s3))] {
if #[cfg(any(esp32c3, esp32c6, esp32s3))] {
unsafe { &*RMT::PTR }
.ch_tx_conf0[$num]
.modify(|_, w| unsafe { w.div_cnt().bits(divider) });
@@ -717,7 +722,7 @@ macro_rules! output_channel {
#[inline(always)]
fn set_carrier_modulation(&mut self, state: bool) -> &mut Self {
cfg_if::cfg_if! {
if #[cfg(any(esp32c3, esp32s3))] {
if #[cfg(any(esp32c3, esp32c6, esp32s3))] {
unsafe { &*RMT::PTR }
.ch_tx_conf0[$num]
.modify(|_, w| w.carrier_en().bit(state));
@@ -845,7 +850,7 @@ macro_rules! rmt {

impl<'d> PulseControl<'d> {
/// Create a new pulse controller instance
#[cfg(any(esp32c3, esp32s3))]
#[cfg(any(esp32c3, esp32c6, esp32s3))]
pub fn new(
instance: impl Peripheral<P = RMT> + 'd,
peripheral_clock_control: &mut PeripheralClockControl,
@@ -902,7 +907,7 @@ macro_rules! rmt {
/// clock is calculated as follows:
///
/// divider = absolute_part + 1 + (fractional_part_a / fractional_part_b)
#[cfg(any(esp32c3, esp32s3))]
#[cfg(any(esp32c3, esp32c6, esp32s3))]
fn config_global(
&self,
clk_source: ClockSource,
@@ -1018,7 +1023,7 @@ macro_rules! rmt {
};
}

#[cfg(esp32c3)]
#[cfg(any(esp32c3, esp32c6))]
rmt!(
sys_conf,
(0, Channel0, channel0, OutputSignal::RMT_SIG_0),
4 changes: 3 additions & 1 deletion esp-hal-common/src/utils/smart_leds_adapter.rs
Original file line number Diff line number Diff line change
@@ -31,6 +31,8 @@ use crate::{
// #44 have been addressed.
#[cfg(esp32c3)]
const SOURCE_CLK_FREQ: u32 = 40_000_000;
#[cfg(esp32c6)]
const SOURCE_CLK_FREQ: u32 = 40_000_000;
#[cfg(esp32s2)]
const SOURCE_CLK_FREQ: u32 = 40_000_000;
#[cfg(esp32)]
@@ -99,7 +101,7 @@ where
where
UnconfiguredChannel: OutputChannel<ConfiguredChannel<'d, O> = CHANNEL>,
{
#[cfg(any(esp32c3, esp32s3))]
#[cfg(any(esp32c3, esp32c6, esp32s3))]
channel
.set_idle_output_level(false)
.set_carrier_modulation(false)