The SPI_CS_SETUP parameter has been observed set by RTOS SDK and NONOS SDK
as part of flash init/configuration. It may be necessary for some flash
chips to perform correctly with ICACHE hardware access. Turning on and
leaving it on should be okay.

Some flash chips (PUYA) have some unknown requirements for running with
early `Cache_Read_Enable`. They work fine after the SDK is started.
For now, change umm_init to default to IRAM.
Define UMM_INIT_USE_ICACHE to move to ICACHE and free up IRAM.

Added some experimental code that may indirectly support PUYA.

Note, until this issue is resolved, that HWDT Stack Dump is not
going to work with PUYA flash.

This resolves the exception 0 issue with PUYA flash when using
flash/ICACHE for umm_init and/or using HWDT Stack Dump.