system: Add complete support for disabling ROM logging by calling esp…

…_deep_sleep_disable_rom_logging on C2, C3, and S3
espressif · Jan 17, 2023 · c7c2462 · c7c2462
1 parent 2c9aa45
commit c7c2462
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Showing 5 changed files with 50 additions and 10 deletions.
diff --git a/components/hal/esp32c2/include/hal/clk_tree_ll.h b/components/hal/esp32c2/include/hal/clk_tree_ll.h
@@ -508,10 +508,18 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
  * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit
  * halves. These are the routines to work with that representation.
  *
- * @param xtal_freq_mhz XTAL frequency, in MHz
+ * @param xtal_freq_mhz XTAL frequency, in MHz. The frequency must necessarily be even,
+ * otherwise there will be a conflict with the low bit, which is used to disable logs
+ * in the ROM code.
  */
 static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
 {
+    // Read the status of whether disabling logging from ROM code
+    uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
+    // If so, need to write back this setting
+    if (reg == RTC_DISABLE_ROM_LOG) {
+        xtal_freq_mhz |= 1;
+    }
     WRITE_PERI_REG(RTC_XTAL_FREQ_REG, (xtal_freq_mhz & UINT16_MAX) | ((xtal_freq_mhz & UINT16_MAX) << 16));
 }
 
@@ -529,7 +537,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(
     uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
     if ((xtal_freq_reg & 0xFFFF) == ((xtal_freq_reg >> 16) & 0xFFFF) &&
         xtal_freq_reg != 0 && xtal_freq_reg != UINT32_MAX) {
-        return xtal_freq_reg & UINT16_MAX;
+        return xtal_freq_reg & ~RTC_DISABLE_ROM_LOG & UINT16_MAX;
     }
     // If the format in reg is invalid
     return 0;

diff --git a/components/hal/esp32c3/include/hal/clk_tree_ll.h b/components/hal/esp32c3/include/hal/clk_tree_ll.h
@@ -615,10 +615,18 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
  * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit
  * halves. These are the routines to work with that representation.
  *
- * @param xtal_freq_mhz XTAL frequency, in MHz
+ * @param xtal_freq_mhz XTAL frequency, in MHz. The frequency must necessarily be even,
+ * otherwise there will be a conflict with the low bit, which is used to disable logs
+ * in the ROM code.
  */
 static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
 {
+    // Read the status of whether disabling logging from ROM code
+    uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
+    // If so, need to write back this setting
+    if (reg == RTC_DISABLE_ROM_LOG) {
+        xtal_freq_mhz |= 1;
+    }
     WRITE_PERI_REG(RTC_XTAL_FREQ_REG, (xtal_freq_mhz & UINT16_MAX) | ((xtal_freq_mhz & UINT16_MAX) << 16));
 }
 
@@ -636,7 +644,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(
     uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
     if ((xtal_freq_reg & 0xFFFF) == ((xtal_freq_reg >> 16) & 0xFFFF) &&
         xtal_freq_reg != 0 && xtal_freq_reg != UINT32_MAX) {
-        return xtal_freq_reg & UINT16_MAX;
+        return xtal_freq_reg & ~RTC_DISABLE_ROM_LOG & UINT16_MAX;
     }
     // If the format in reg is invalid
     return 0;

diff --git a/components/hal/esp32c6/include/hal/clk_tree_ll.h b/components/hal/esp32c6/include/hal/clk_tree_ll.h
@@ -718,10 +718,18 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
  * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit
  * halves. These are the routines to work with that representation.
  *
- * @param xtal_freq_mhz XTAL frequency, in MHz
+ * @param xtal_freq_mhz XTAL frequency, in MHz. The frequency must necessarily be even,
+ * otherwise there will be a conflict with the low bit, which is used to disable logs
+ * in the ROM code.
  */
 static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
 {
+    // Read the status of whether disabling logging from ROM code
+    uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
+    // If so, need to write back this setting
+    if (reg == RTC_DISABLE_ROM_LOG) {
+        xtal_freq_mhz |= 1;
+    }
     WRITE_PERI_REG(RTC_XTAL_FREQ_REG, (xtal_freq_mhz & UINT16_MAX) | ((xtal_freq_mhz & UINT16_MAX) << 16));
 }
 
@@ -739,7 +747,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(
     uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
     if ((xtal_freq_reg & 0xFFFF) == ((xtal_freq_reg >> 16) & 0xFFFF) &&
         xtal_freq_reg != 0 && xtal_freq_reg != UINT32_MAX) {
-        return xtal_freq_reg & UINT16_MAX;
+        return xtal_freq_reg & ~RTC_DISABLE_ROM_LOG & UINT16_MAX;
     }
     // If the format in reg is invalid
     return 0;

diff --git a/components/hal/esp32h4/include/hal/clk_tree_ll.h b/components/hal/esp32h4/include/hal/clk_tree_ll.h
@@ -503,10 +503,18 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
  * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit
  * halves. These are the routines to work with that representation.
  *
- * @param xtal_freq_mhz XTAL frequency, in MHz
+ * @param xtal_freq_mhz XTAL frequency, in MHz. The frequency must necessarily be even,
+ * otherwise there will be a conflict with the low bit, which is used to disable logs
+ * in the ROM code.
  */
 static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
 {
+    // Read the status of whether disabling logging from ROM code
+    uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
+    // If so, need to write back this setting
+    if (reg == RTC_DISABLE_ROM_LOG) {
+        xtal_freq_mhz |= 1;
+    }
     WRITE_PERI_REG(RTC_XTAL_FREQ_REG, (xtal_freq_mhz & UINT16_MAX) | ((xtal_freq_mhz & UINT16_MAX) << 16));
 }
 
@@ -522,7 +530,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(
 {
     // ESP32H4 has a fixed crystal frequency (32MHz), but we will still read from the RTC storage register
     uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
-    if ((xtal_freq_reg & UINT16_MAX) != RTC_XTAL_FREQ_32M) {
+    if ((xtal_freq_reg & ~RTC_DISABLE_ROM_LOG & UINT16_MAX) != RTC_XTAL_FREQ_32M) {
         return 0;
     }
     return (uint32_t)RTC_XTAL_FREQ_32M;

diff --git a/components/hal/esp32s3/include/hal/clk_tree_ll.h b/components/hal/esp32s3/include/hal/clk_tree_ll.h
@@ -622,10 +622,18 @@ static inline void clk_ll_rc_slow_set_divider(uint32_t divider)
  * Value of RTC_XTAL_FREQ_REG is stored as two copies in lower and upper 16-bit
  * halves. These are the routines to work with that representation.
  *
- * @param xtal_freq_mhz XTAL frequency, in MHz
+ * @param xtal_freq_mhz XTAL frequency, in MHz. The frequency must necessarily be even,
+ * otherwise there will be a conflict with the low bit, which is used to disable logs
+ * in the ROM code.
  */
 static inline void clk_ll_xtal_store_freq_mhz(uint32_t xtal_freq_mhz)
 {
+    // Read the status of whether disabling logging from ROM code
+    uint32_t reg = READ_PERI_REG(RTC_XTAL_FREQ_REG) & RTC_DISABLE_ROM_LOG;
+    // If so, need to write back this setting
+    if (reg == RTC_DISABLE_ROM_LOG) {
+        xtal_freq_mhz |= 1;
+    }
     WRITE_PERI_REG(RTC_XTAL_FREQ_REG, (xtal_freq_mhz & UINT16_MAX) | ((xtal_freq_mhz & UINT16_MAX) << 16));
 }
 
@@ -643,7 +651,7 @@ static inline __attribute__((always_inline)) uint32_t clk_ll_xtal_load_freq_mhz(
     uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
     if ((xtal_freq_reg & 0xFFFF) == ((xtal_freq_reg >> 16) & 0xFFFF) &&
         xtal_freq_reg != 0 && xtal_freq_reg != UINT32_MAX) {
-        return xtal_freq_reg & UINT16_MAX;
+        return xtal_freq_reg & ~RTC_DISABLE_ROM_LOG & UINT16_MAX;
     }
     // If the format in reg is invalid
     return 0;