SRL16 support #961

mkurc-ant · 2019-08-23T14:11:31Z

Add support for SRL16 to VPR and fasm2bels with timings.

litghost

Looks awesome! Just some small comments.

litghost · 2019-09-04T17:40:17Z

xc7/fasm2bels/clb_models.py


-    if carry4 is None:
-        return
+        # Simplest check is if the CARRY4 has output in used by either the OUTMUX


Let's refactor the cleanup into "cleanup_carry4", "cleanup_srl", assuming that no logic/data is shared between them.

litghost · 2019-09-04T17:41:19Z

xc7/primitives/slicem/slicem.pb_type.xml

        <direct name="SLICEM_MODES.CE_to_WE_MUX.CE" input="SLICEM_MODES.CE" output="WE_MUX.CE"/>
-        <direct name="SLICEM_MODES.WE_to_WE_MUX.WE" input="SLICEM_MODES.WE" output="WE_MUX.WE"/>


Why force CE over WE here?

This is to maintain compatibility with Vivado which cannot route through WE to an SRL.

There is no such limitation in hardware, both CE and WE work. However, when trying to import disassembled fasm with routing through WE, Vivado refuses to use that input which results in "antenna net" error.

I added more elaborate comment to the file.

You have misinterpreted the error. Vivado can route using the WE to the SRL, but will generally refuse if the CE port is available. The example to check is have the SRL CE and FF CE use different net's, but force them to pack into the same SLICEM.

Ok, I'll check that tomorrow. But still, if I enable WE there will be issues with importing the VPR routing back to Vivado in case when there is only SRL in a slice.

The solution to this problem is have VPR choose CE over WE, either by making sure it is the default (e.g. first in the <mux>) or by some timing pressure. Presumably Vivado chooses CE over WE for that reason.

I've re-enabled the WE input of WEMUX.

Actually, the CE input should be the default as it is defined in the XML:

<mux name="WE_MUX" input="WE_MUX.CE WE_MUX.WE" output="WE_MUX.WE_OUT"> <metadata> <meta name="fasm_mux"> WE_MUX.CE = WEMUX.CE WE_MUX.WE = NULL </meta> </metadata> </mux>

litghost · 2019-09-04T17:41:45Z

xc7/primitives/slicem/srl/a_srl.pb_type.xml

@@ -0,0 +1,65 @@
+<pb_type name="ASRL" num_pb="1" xmlns:xi="http://www.w3.org/2001/XInclude">


Please add a comment on why the a_srl is special, for future reference.

It is special because it requires different pack patterns for chaining. I added comment at the beginning of the file.

xc7/techmap/cells_map.v

…use VPR complained about them. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

…ing. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

…s for SRL16 (some). Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

…Yosys!). Reenabled testbinch for srl16_amc31 Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

…with Vivado which can't route through WE. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

litghost · 2019-09-06T23:39:29Z

xc7/tests/srl/srl16_amc31/CMakeLists.txt

@@ -0,0 +1,46 @@
+add_file_target(FILE basys3_doutmux_top.v SCANNER_TYPE verilog)
+#add_file_target(FILE basys3_dffmux_top.v SCANNER_TYPE verilog)


Why are the dffmux tests commented out?

That is because I cannot verify it on hardware. The VPR refuses to use FF on the same slice as the SRL. I'll try to play more with pack patterns, maybe I can get it to do so.

@litghost I discovered that in order to have such a pack pattern we would need to make different COMMON_SLICE and SLICE_FF pb_types for SLICEL and SLICEM. That is because MC31 related pack patterns cannot be specified inside SLICEL as this makes VPR report an error.

I made specialized COMMON_SLICE and SLICE_FF but still couldn't force VPR to pack SRL and FF in the same slice.

I think that having the DFFMUX.MC31 working is not a top priority. I can file an issue with a description what (supposedly) needs to be done.

I think that having the DFFMUX.MC31 working is not a top priority. I can file an issue with a description what (supposedly) needs to be done.

This makes sense to me for now. File the issue, add a FIXME near this comment, and then LGTM.

I added comments to CMake files. There is the issue: #974

litghost

Assuming this is working on hardware, LGTM

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

…es/third_party/symbiyosys-43a7996 build(deps): bump third_party/symbiyosys from `adacad7` to `43a7996`

mkurc-ant force-pushed the srl16_support branch 3 times, most recently from 096bcf4 to 19bec32 Compare August 27, 2019 10:39

mkurc-ant changed the title ~~[DNM] [WIP] SRL16 support~~ SRL16 support Aug 27, 2019

mkurc-ant requested a review from litghost August 27, 2019 16:29

mkurc-ant force-pushed the srl16_support branch from 625da30 to cf83d4a Compare September 2, 2019 08:43

litghost suggested changes Sep 4, 2019

View reviewed changes

mkurc-ant added the kokoro:force-run label Sep 5, 2019

mkurc-ant added 16 commits September 5, 2019 10:56

Initial SRL16 support. Works on HW. Had to disable pack patterns beca…

fca9b74

…use VPR complained about them. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Initialization support for SRL16. Working on HW.

8b1129b

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Re-enabled pack patterns for chaining SRL32s

6d97e2c

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added test for MC31 output for upper half of ASRL in SRL16 mode. Work…

1e4a81b

…ing. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Disabled testbinch targets as fasm2v does not support SRL16 yet

0cf86fe

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Preliminary support for SRL16 for fasm2bels. Reenabled testbinch test…

c321eca

…s for SRL16 (some). Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added simulation model of SRLC16E to cells_sim.v (should be moved to …

240363b

…Yosys!). Reenabled testbinch for srl16_amc31 Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added SRL16/SRL32 chaining test.

ad4be9c

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added conditional include of SRLC32E cell definition.

78b1dfc

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Fixed build system, added non-zero INIT for const-0 generating LUTs.

0a59eed

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Fixed unused inputs in srl16_chain_test

a964a71

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added removal of unused SRL16 (cleanup) to fasm2bels

e7302c3

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Forced routing of nSRL.WE input through CE to maintain compatibility …

8212739

…with Vivado which can't route through WE. Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Added timing information to SRL16.

ae953cd

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Documentation.

be5aaed

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

Refactored slice cleanup code.

47a7986

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

mkurc-ant force-pushed the srl16_support branch from ddd13f8 to 47a7986 Compare September 5, 2019 08:59

kokoro-team removed the kokoro:force-run label Sep 5, 2019

Re-enabled VPR routing through WEMUX.WE for SRLs.

10454a2

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

litghost mentioned this pull request Sep 6, 2019

[Branch] disable-srl16 SymbiFlow/yosys#38

Open

litghost reviewed Sep 6, 2019

View reviewed changes

litghost approved these changes Sep 6, 2019

View reviewed changes

Added comments regarding why SRL DFFMUX.MC31 tests are disabled.

fd60b45

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

litghost merged commit 04cadc7 into f4pga:master Sep 10, 2019

This was referenced Sep 12, 2019

[xc7/fasm2v] Support SRL16/32 #903

Closed

Add support for SRL16/SRL32 #835

Closed

mkurc-ant deleted the srl16_support branch November 20, 2019 09:24

mkurc-ant pushed a commit to antmicro/f4pga-arch-defs that referenced this pull request Apr 6, 2022

Merge pull request f4pga#961 from QuickLogic-Corp/dependabot/submodul…

50ad9a4

…es/third_party/symbiyosys-43a7996 build(deps): bump third_party/symbiyosys from `adacad7` to `43a7996`

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SRL16 support #961

SRL16 support #961

mkurc-ant commented Aug 23, 2019 •

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		<direct name="SLICEM_MODES.CE_to_WE_MUX.CE" input="SLICEM_MODES.CE" output="WE_MUX.CE"/>
		<direct name="SLICEM_MODES.WE_to_WE_MUX.WE" input="SLICEM_MODES.WE" output="WE_MUX.WE"/>

		@@ -0,0 +1,65 @@
		<pb_type name="ASRL" num_pb="1" xmlns:xi="http://www.w3.org/2001/XInclude">

		@@ -0,0 +1,46 @@
		add_file_target(FILE basys3_doutmux_top.v SCANNER_TYPE verilog)
		#add_file_target(FILE basys3_dffmux_top.v SCANNER_TYPE verilog)

SRL16 support #961

SRL16 support #961

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mkurc-ant commented Aug 23, 2019 •

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