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fby3.5: rf: Update the GPIO configurations. #374

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Scron-Chang
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@Scron-Chang Scron-Chang commented Jul 1, 2022

  • Change the configurations of default state, output type, direction:

    • GPIOA2:
      Set GPIOA2 as default low to not enable the recovery mode of the
      CXL controller.

    • GPIOA6:
      Set as output and default high because BIC may need to reset JTAG
      directly in a particular case.

    • GPIOA7:
      Set as default low to set the JTAG mode.

    • GPIOB1:
      Set as default low to set CXL controller boots from its own ROM in
      the default situation.

    • GPIOB3:
      Set as input to not control the CXL controller GPIO_0.

    • GPIOB6:
      Set as default high to avoid resetting the I2C interface of the
      CXL controller when BIC reboots.

    • GPIOF0:
      Set as default high and open-drain output type. This pin controls
      the flash memory which uses 1.8V.

    • GPIOF1:
      Set as default high to match the default HW state.

    • GPIOH2:
      Set as Output and default low to enable the SPI buffer in the
      default mode.

  • Enable the latch feature for the following GPIOs to avoid making
    unexpected consequences:

    • GPIOA0/1:
      These two pins trigger the cold and warm reset signal on the CXL
      controller, respectively.

    • GPIOC0~D1:
      These pin control the power deliver.

    • GPIOE1:
      This pin is used to inform the mainboard that Rainbow Falls is
      ready.

    • GPIOF2:
      This pin controls the buffer handling the voltage shift.

Tested:

  • Rainbow Falls platfrom build: Pass.
  • BIC warm reboot doesn't affect the PM8702. I have verified this from
    the PM8702 console.
  • Console logs from the RF BIC:
[set_MB_DC_status] gpio number(32) status(1)
[control_power_on_sequence] power on success
[set_DC_status] gpio number(33) status(1)

uart:~$ platform gpio list_all
[0  ] ASIC_DEV_RST_N                     : OD  | output(I) | 1(1)
[1  ] ASIC_PERST0_N                      : OD  | output(I) | 1(1)
[2  ] ASIC_PERST1_N                      : OD  | output(O) | 0(0)
[6  ] JTAG2_BIC_ASIC_NTRST2              : PP  | output(O) | 1(1)
[7  ] ASIC_TAP_SEL                       : OD  | output(O) | 0(0)
[9  ] ASIC_CPU_BOOT_1                    : OD  | output(O) | 0(0)
[11 ] ASIC_GPIO_R_0                      : OD  | input (I) | 1(1)
[14 ] I2CS_SRSTB_GPIO                    : OD  | output(I) | 1(1)
[35 ] SPI_MASTER_SEL                     : PP  | output(O) | 0(0)
[40 ] SPI_RST_FLASH_N                    : OD  | output(I) | 0(0)
[41 ] SMBUS_ALERT_R_N                    : OD  | output(I) | 1(1)
[58 ] SPI_BIC_SHIFT_EN                   : OD  | output(O) | 0(0)

Signed-off-by: Scron Chang Scron.Chang@quantatw.com

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@Scron-Chang Scron-Chang force-pushed the dev_scron_RF_Update_GPIO_config branch 2 times, most recently from a2fda1c to 85673c1 Compare July 5, 2022 08:29
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@Scron-Chang

Hello, Could you please complete the CLA. It's not possible to continue until that is finished.

@Scron-Chang
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Hi @GoldenBug,
Sorry for the confusion. My CLA is now under process.

meta-facebook/yv35-rf/src/platform/plat_gpio.c Outdated Show resolved Hide resolved
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@Scron-Chang Scron-Chang force-pushed the dev_scron_RF_Update_GPIO_config branch 3 times, most recently from a6819be to 4473cff Compare July 12, 2022 07:03
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I rebased this branch and updated the description of this PR. In addition, I removed the log of the BIC console because the RainbowFalls board I am using is incomplete and could cause confusion to the reviewer. If I get the complete RainbowFalls, I will check this PR with it immediately.

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Any updates on the CLA?

@Scron-Chang Scron-Chang force-pushed the dev_scron_RF_Update_GPIO_config branch from 4473cff to a142186 Compare July 19, 2022 06:52
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Any updates on the CLA?

My manager has sent a mail for my CLA, but we don't receive any response from Meta. Would you kindly check the email box for that?

@Scron-Chang
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I received the Rainbow Falls board. I updated the code based on the suggestions from @GoldenBug and tested it. Also, the description of this PR has been updated. There now are the result of the gpio list and the reaction of PM8702 when BIC reboots.

@facebook-github-bot facebook-github-bot added the CLA Signed This label is managed by the Facebook bot. Authors need to sign the CLA before a PR can be reviewed. label Aug 2, 2022
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Thank you for signing our Contributor License Agreement. We can now accept your code for this (and any) Meta Open Source project. Thanks!

- Change the configurations of default state, output type, direction:

    - GPIOA2:
      Set GPIOA2 as default low to not enable the recovery mode of the
      CXL controller.

    - GPIOA6:
      Set as output and default high because BIC may need to reset JTAG
      directly in a particular case.

    - GPIOA7:
      Set as default low to set the JTAG mode.

    - GPIOB1:
      Set as default low to set CXL controller boots from its own ROM in
      the default situation.

    - GPIOB3:
      Set as input to not control the CXL controller GPIO_0.

    - GPIOB6:
      Set as default high to avoid resetting the I2C interface of the
      CXL controller when BIC reboots.

    - GPIOF0:
      Set as default high and open-drain output type. This pin controls
      the flash memory which uses 1.8V.

    - GPIOF1:
      Set as default high to match the default HW state.

    - GPIOH2:
      Set as Output and default low to enable the SPI buffer in the
      default mode.

- Enable the latch feature for the following GPIOs to avoid making
  unexpected consequences:

    - GPIOA0/1:
      These two pins trigger the cold and warm reset signal on the CXL
      controller, respectively.

    - GPIOC0~D1:
      These pin control the power deliver.

    - GPIOE1:
      This pin is used to inform the mainboard that Rainbow Falls is
      ready.

    - GPIOF2:
      This pin controls the buffer handling the voltage shift.

Tested:
- Rainbow Falls platfrom build: Pass.
- BIC warm reboot doesn't affect the PM8702. I have verified this from
  the PM8702 console.
- Console logs from the RF BIC:
```
[set_MB_DC_status] gpio number(32) status(1)
[control_power_on_sequence] power on success
[set_DC_status] gpio number(33) status(1)

uart:~$ platform gpio list_all
[0  ] ASIC_DEV_RST_N                     : OD  | output(I) | 1(1)
[1  ] ASIC_PERST0_N                      : OD  | output(I) | 1(1)
[2  ] ASIC_PERST1_N                      : OD  | output(O) | 0(0)
[6  ] JTAG2_BIC_ASIC_NTRST2              : PP  | output(O) | 1(1)
[7  ] ASIC_TAP_SEL                       : OD  | output(O) | 0(0)
[9  ] ASIC_CPU_BOOT_1                    : OD  | output(O) | 0(0)
[11 ] ASIC_GPIO_R_0                      : OD  | input (I) | 1(1)
[14 ] I2CS_SRSTB_GPIO                    : OD  | output(I) | 1(1)
[35 ] SPI_MASTER_SEL                     : PP  | output(O) | 0(0)
[40 ] SPI_RST_FLASH_N                    : OD  | output(I) | 0(0)
[41 ] SMBUS_ALERT_R_N                    : OD  | output(I) | 1(1)
[58 ] SPI_BIC_SHIFT_EN                   : OD  | output(O) | 0(0)
```

Signed-off-by: Scron Chang <Scron.Chang@quantatw.com>
@Scron-Chang Scron-Chang force-pushed the dev_scron_RF_Update_GPIO_config branch from a142186 to e3f85a5 Compare August 3, 2022 00:57
@Scron-Chang
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Hi @GoldenBug ,
I feel excited I just got the CLA.
I just rebased this PR. Please review it again. Appreciate.

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@garnermic has imported this pull request. If you are a Meta employee, you can view this diff on Phabricator.

@Scron-Chang Scron-Chang deleted the dev_scron_RF_Update_GPIO_config branch August 3, 2022 23:30
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3 participants