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@falsandtru
falsandtru committed Feb 17, 2024
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274 changes: 200 additions & 74 deletions README.md
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Original file line number Diff line number Diff line change
Expand Up @@ -28,161 +28,287 @@ It is verified that the error was thrown also when benchmarking only lru-cache.
Clock: spica/clock<br>
ISCCache: [lru-cache](https://www.npmjs.com/package/lru-cache)<br>
LRUCache: spica/lru<br>
TRC-C: spica/tlru (spica/trul.clock)<br>
TRC-L: spica/trul.lru<br>
DW-Cache: spica/cache<br>

```
'Clock new x 1,650,836 ops/sec ±1.94% (94 runs sampled)'
'Clock new x 1,762,855 ops/sec ±3.54% (110 runs sampled)'
'ISCCache new x 18,042 ops/sec ±0.66% (105 runs sampled)'
'ISC new x 18,054 ops/sec ±0.46% (120 runs sampled)'
'LRUCache new x 30,098,951 ops/sec ±0.23% (106 runs sampled)'
'LRU new x 26,663,820 ops/sec ±0.95% (122 runs sampled)'
'DW-Cache new x 7,021,323 ops/sec ±0.30% (105 runs sampled)'
'TRC-C new x 25,456,476 ops/sec ±1.33% (121 runs sampled)'
'Clock simulation 100 10% x 9,762,593 ops/sec ±0.36% (107 runs sampled)'
'TRC-L new x 25,456,051 ops/sec ±1.20% (121 runs sampled)'
'ISCCache simulation 100 10% x 8,761,469 ops/sec ±0.38% (107 runs sampled)'
'DWC new x 6,660,939 ops/sec ±0.46% (122 runs sampled)'
'LRUCache simulation 100 10% x 10,769,407 ops/sec ±0.28% (107 runs sampled)'
'Clock simulation 100 10% x 9,414,387 ops/sec ±0.63% (122 runs sampled)'
'DW-Cache simulation 100 10% x 7,242,192 ops/sec ±0.50% (105 runs sampled)'
'ISC simulation 100 10% x 8,984,969 ops/sec ±0.72% (121 runs sampled)'
'Clock simulation 1,000 10% x 9,601,967 ops/sec ±0.48% (107 runs sampled)'
'LRU simulation 100 10% x 10,790,718 ops/sec ±0.37% (122 runs sampled)'
'ISCCache simulation 1,000 10% x 7,986,140 ops/sec ±0.58% (106 runs sampled)'
'TRC-C simulation 100 10% x 10,583,002 ops/sec ±0.54% (122 runs sampled)'
'LRUCache simulation 1,000 10% x 9,735,550 ops/sec ±0.41% (106 runs sampled)'
'TRC-L simulation 100 10% x 9,622,956 ops/sec ±0.46% (123 runs sampled)'
'DW-Cache simulation 1,000 10% x 6,592,345 ops/sec ±0.37% (107 runs sampled)'
'DWC simulation 100 10% x 6,899,358 ops/sec ±0.52% (122 runs sampled)'
'Clock simulation 10,000 10% x 9,344,809 ops/sec ±0.40% (105 runs sampled)'
'Clock simulation 1,000 10% x 9,403,202 ops/sec ±0.50% (122 runs sampled)'
'ISCCache simulation 10,000 10% x 7,193,304 ops/sec ±0.83% (106 runs sampled)'
'ISC simulation 1,000 10% x 8,281,707 ops/sec ±0.68% (123 runs sampled)'
'LRUCache simulation 10,000 10% x 8,881,517 ops/sec ±0.41% (104 runs sampled)'
'LRU simulation 1,000 10% x 9,390,248 ops/sec ±0.64% (122 runs sampled)'
'DW-Cache simulation 10,000 10% x 6,020,040 ops/sec ±0.50% (106 runs sampled)'
'TRC-C simulation 1,000 10% x 9,371,450 ops/sec ±0.60% (122 runs sampled)'
'Clock simulation 100,000 10% x 5,948,133 ops/sec ±1.22% (101 runs sampled)'
'TRC-L simulation 1,000 10% x 8,769,717 ops/sec ±0.42% (122 runs sampled)'
'ISCCache simulation 100,000 10% x 3,654,505 ops/sec ±1.47% (101 runs sampled)'
'DWC simulation 1,000 10% x 6,880,442 ops/sec ±0.61% (123 runs sampled)'
'LRUCache simulation 100,000 10% x 5,615,930 ops/sec ±1.35% (100 runs sampled)'
'Clock simulation 10,000 10% x 9,365,785 ops/sec ±0.44% (121 runs sampled)'
'DW-Cache simulation 100,000 10% x 4,255,377 ops/sec ±1.79% (97 runs sampled)'
'ISC simulation 10,000 10% x 6,765,160 ops/sec ±0.72% (122 runs sampled)'
'Clock simulation 1,000,000 10% x 2,605,647 ops/sec ±3.98% (93 runs sampled)'
'LRU simulation 10,000 10% x 8,766,599 ops/sec ±0.85% (121 runs sampled)'
'ISCCache simulation 1,000,000 10% x 1,453,643 ops/sec ±2.92% (95 runs sampled)'
'TRC-C simulation 10,000 10% x 8,518,274 ops/sec ±1.50% (121 runs sampled)'
'LRUCache simulation 1,000,000 10% x 2,081,983 ops/sec ±4.23% (88 runs sampled)'
'TRC-L simulation 10,000 10% x 7,622,128 ops/sec ±0.60% (121 runs sampled)'
'DW-Cache simulation 1,000,000 10% x 2,598,274 ops/sec ±4.42% (89 runs sampled)'
'DWC simulation 10,000 10% x 5,847,304 ops/sec ±0.85% (122 runs sampled)'
'Clock simulation 100 90% x 25,014,146 ops/sec ±0.33% (107 runs sampled)'
'Clock simulation 100,000 10% x 5,800,245 ops/sec ±1.68% (115 runs sampled)'
'ISCCache simulation 100 90% x 22,495,828 ops/sec ±0.74% (105 runs sampled)'
'ISC simulation 100,000 10% x 3,428,512 ops/sec ±1.36% (116 runs sampled)'
'LRUCache simulation 100 90% x 20,969,655 ops/sec ±0.84% (107 runs sampled)'
'LRU simulation 100,000 10% x 5,286,012 ops/sec ±2.12% (113 runs sampled)'
'DW-Cache simulation 100 90% x 9,730,398 ops/sec ±0.32% (107 runs sampled)'
'TRC-C simulation 100,000 10% x 5,640,959 ops/sec ±2.43% (112 runs sampled)'
'Clock simulation 1,000 90% x 23,025,311 ops/sec ±0.51% (107 runs sampled)'
'TRC-L simulation 100,000 10% x 4,929,609 ops/sec ±2.54% (112 runs sampled)'
'ISCCache simulation 1,000 90% x 19,347,819 ops/sec ±0.34% (107 runs sampled)'
'DWC simulation 100,000 10% x 3,803,619 ops/sec ±2.14% (107 runs sampled)'
'LRUCache simulation 1,000 90% x 18,240,448 ops/sec ±0.28% (107 runs sampled)'
'Clock simulation 1,000,000 10% x 2,652,173 ops/sec ±3.13% (103 runs sampled)'
'DW-Cache simulation 1,000 90% x 11,382,934 ops/sec ±0.19% (108 runs sampled)'
'ISC simulation 1,000,000 10% x 1,460,486 ops/sec ±3.66% (105 runs sampled)'
'Clock simulation 10,000 90% x 20,506,917 ops/sec ±0.25% (105 runs sampled)'
'LRU simulation 1,000,000 10% x 2,099,026 ops/sec ±4.48% (95 runs sampled)'
'ISCCache simulation 10,000 90% x 15,441,103 ops/sec ±1.24% (105 runs sampled)'
'TRC-C simulation 1,000,000 10% x 2,111,358 ops/sec ±5.19% (92 runs sampled)'
'LRUCache simulation 10,000 90% x 13,104,661 ops/sec ±0.61% (105 runs sampled)'
'TRC-L simulation 1,000,000 10% x 2,027,782 ops/sec ±4.41% (96 runs sampled)'
'DW-Cache simulation 10,000 90% x 8,747,757 ops/sec ±0.92% (107 runs sampled)'
'DWC simulation 1,000,000 10% x 2,524,424 ops/sec ±4.58% (97 runs sampled)'
'Clock simulation 100,000 90% x 12,049,875 ops/sec ±1.49% (100 runs sampled)'
'Clock simulation 100 90% x 20,881,968 ops/sec ±0.85% (121 runs sampled)'
'ISCCache simulation 100,000 90% x 8,173,371 ops/sec ±1.17% (102 runs sampled)'
'ISC simulation 100 90% x 19,882,887 ops/sec ±0.62% (121 runs sampled)'
'LRUCache simulation 100,000 90% x 8,188,424 ops/sec ±2.08% (100 runs sampled)'
'LRU simulation 100 90% x 19,270,216 ops/sec ±0.77% (122 runs sampled)'
'DW-Cache simulation 100,000 90% x 5,973,422 ops/sec ±2.65% (100 runs sampled)'
'TRC-C simulation 100 90% x 18,564,258 ops/sec ±0.55% (122 runs sampled)'
'Clock simulation 1,000,000 90% x 5,578,321 ops/sec ±4.20% (92 runs sampled)'
'TRC-L simulation 100 90% x 16,936,115 ops/sec ±0.63% (122 runs sampled)'
'ISCCache simulation 1,000,000 90% x 2,963,294 ops/sec ±2.91% (95 runs sampled)'
'DWC simulation 100 90% x 8,753,497 ops/sec ±0.42% (122 runs sampled)'
'LRUCache simulation 1,000,000 90% x 2,235,658 ops/sec ±2.83% (95 runs sampled)'
'Clock simulation 1,000 90% x 19,710,867 ops/sec ±0.67% (122 runs sampled)'
'DW-Cache simulation 1,000,000 90% x 1,931,442 ops/sec ±2.32% (98 runs sampled)'
'ISC simulation 1,000 90% x 17,133,972 ops/sec ±0.54% (121 runs sampled)'
'ISCCache simulation 100 90% expire x 4,172,541 ops/sec ±5.34% (94 runs sampled)'
'LRU simulation 1,000 90% x 16,805,166 ops/sec ±0.72% (121 runs sampled)'
'DW-Cache simulation 100 90% expire x 8,241,722 ops/sec ±0.42% (107 runs sampled)'
'TRC-C simulation 1,000 90% x 16,661,753 ops/sec ±0.63% (122 runs sampled)'
'ISCCache simulation 1,000 90% expire x 4,169,949 ops/sec ±3.98% (97 runs sampled)'
'TRC-L simulation 1,000 90% x 15,223,439 ops/sec ±0.55% (123 runs sampled)'
'DW-Cache simulation 1,000 90% expire x 8,218,212 ops/sec ±0.30% (107 runs sampled)'
'DWC simulation 1,000 90% x 8,646,913 ops/sec ±0.40% (122 runs sampled)'
'ISCCache simulation 10,000 90% expire x 3,539,574 ops/sec ±4.02% (98 runs sampled)'
'Clock simulation 10,000 90% x 17,716,331 ops/sec ±0.70% (121 runs sampled)'
'DW-Cache simulation 10,000 90% expire x 6,338,384 ops/sec ±1.07% (105 runs sampled)'
'ISC simulation 10,000 90% x 14,133,454 ops/sec ±0.77% (122 runs sampled)'
'ISCCache simulation 100,000 90% expire x 2,429,074 ops/sec ±4.48% (94 runs sampled)'
'LRU simulation 10,000 90% x 12,002,433 ops/sec ±1.28% (120 runs sampled)'
'DW-Cache simulation 100,000 90% expire x 1,977,169 ops/sec ±2.71% (86 runs sampled)'
'TRC-C simulation 10,000 90% x 11,484,228 ops/sec ±0.61% (121 runs sampled)'
'ISCCache simulation 1,000,000 90% expire x 448,719 ops/sec ±5.09% (82 runs sampled)'
'TRC-L simulation 10,000 90% x 10,433,045 ops/sec ±0.53% (120 runs sampled)'
'DW-Cache simulation 1,000,000 90% expire x 629,254 ops/sec ±3.81% (98 runs sampled)'
'DWC simulation 10,000 90% x 7,453,628 ops/sec ±0.93% (121 runs sampled)'
'Clock simulation 100,000 90% x 10,401,128 ops/sec ±1.42% (115 runs sampled)'
'ISC simulation 100,000 90% x 7,706,599 ops/sec ±1.16% (115 runs sampled)'
'LRU simulation 100,000 90% x 7,391,029 ops/sec ±2.26% (116 runs sampled)'
'TRC-C simulation 100,000 90% x 7,135,837 ops/sec ±2.01% (114 runs sampled)'
'TRC-L simulation 100,000 90% x 6,756,826 ops/sec ±1.97% (115 runs sampled)'
'DWC simulation 100,000 90% x 5,457,505 ops/sec ±1.59% (116 runs sampled)'
'Clock simulation 1,000,000 90% x 4,706,093 ops/sec ±3.22% (104 runs sampled)'
'ISC simulation 1,000,000 90% x 2,765,132 ops/sec ±3.70% (105 runs sampled)'
'LRU simulation 1,000,000 90% x 2,177,354 ops/sec ±2.42% (114 runs sampled)'
'TRC-C simulation 1,000,000 90% x 2,182,726 ops/sec ±2.55% (107 runs sampled)'
'TRC-L simulation 1,000,000 90% x 2,099,229 ops/sec ±2.59% (105 runs sampled)'
'DWC simulation 1,000,000 90% x 1,712,921 ops/sec ±2.24% (112 runs sampled)'
'ISC simulation 100 90% expire x 4,288,276 ops/sec ±4.60% (110 runs sampled)'
'DWC simulation 100 90% expire x 7,340,468 ops/sec ±0.35% (123 runs sampled)'
'ISC simulation 1,000 90% expire x 4,386,285 ops/sec ±3.49% (116 runs sampled)'
'DWC simulation 1,000 90% expire x 6,780,647 ops/sec ±0.62% (122 runs sampled)'
'ISC simulation 10,000 90% expire x 3,837,624 ops/sec ±2.00% (117 runs sampled)'
'DWC simulation 10,000 90% expire x 6,075,286 ops/sec ±1.23% (121 runs sampled)'
'ISC simulation 100,000 90% expire x 2,868,297 ops/sec ±2.94% (112 runs sampled)'
'DWC simulation 100,000 90% expire x 3,122,360 ops/sec ±2.37% (104 runs sampled)'
'ISC simulation 1,000,000 90% expire x 542,304 ops/sec ±5.11% (106 runs sampled)'
'DWC simulation 1,000,000 90% expire x 626,548 ops/sec ±4.23% (100 runs sampled)'
```

Clock outperforms LRU, especially in the get operation by marking algorithm.
Therefore, when the cache is less likely to overflow, Clock is particularly faster than LRU.

```
'Clock get 100 100% x 33,939,567 ops/sec ±0.11% (124 runs sampled)'
'Clock get hit 100 x 27,596,711 ops/sec ±0.99% (122 runs sampled)'
'ISC get hit 100 x 23,631,355 ops/sec ±0.75% (122 runs sampled)'
'LRU get hit 100 x 21,809,759 ops/sec ±0.63% (122 runs sampled)'
'TRC-C get hit 100 x 23,100,835 ops/sec ±1.09% (121 runs sampled)'
'TRC-L get hit 100 x 21,429,424 ops/sec ±0.57% (123 runs sampled)'
'DWC get hit 100 x 14,766,611 ops/sec ±0.66% (122 runs sampled)'
'Clock get hit 1,000 x 27,217,959 ops/sec ±0.98% (121 runs sampled)'
'ISC get hit 1,000 x 21,641,052 ops/sec ±0.70% (122 runs sampled)'
'LRU get hit 1,000 x 19,513,383 ops/sec ±0.90% (121 runs sampled)'
'TRC-C get hit 1,000 x 21,105,948 ops/sec ±0.79% (121 runs sampled)'
'TRC-L get hit 1,000 x 19,310,983 ops/sec ±0.54% (122 runs sampled)'
'DWC get hit 1,000 x 12,912,664 ops/sec ±0.47% (122 runs sampled)'
'Clock get hit 10,000 x 28,196,039 ops/sec ±1.06% (120 runs sampled)'
'ISC get hit 10,000 x 19,915,781 ops/sec ±0.62% (121 runs sampled)'
'LRU get hit 10,000 x 14,099,912 ops/sec ±0.88% (121 runs sampled)'
'TRC-C get hit 10,000 x 14,985,840 ops/sec ±0.90% (121 runs sampled)'
'TRC-L get hit 10,000 x 13,819,010 ops/sec ±0.79% (122 runs sampled)'
'DWC get hit 10,000 x 10,413,001 ops/sec ±0.66% (122 runs sampled)'
'Clock get hit 100,000 x 16,476,192 ops/sec ±1.03% (120 runs sampled)'
'ISC get hit 100,000 x 9,957,174 ops/sec ±0.51% (123 runs sampled)'
'LRU get hit 100,000 x 8,688,197 ops/sec ±0.83% (120 runs sampled)'
'TRC-C get hit 100,000 x 8,852,077 ops/sec ±1.28% (120 runs sampled)'
'TRC-L get hit 100,000 x 8,348,773 ops/sec ±1.07% (121 runs sampled)'
'DWC get hit 100,000 x 7,126,031 ops/sec ±0.83% (122 runs sampled)'
'Clock get hit 1,000,000 x 9,955,039 ops/sec ±1.88% (117 runs sampled)'
'ISC get hit 1,000,000 x 3,906,286 ops/sec ±2.69% (113 runs sampled)'
'LRU get hit 1,000,000 x 2,415,531 ops/sec ±1.47% (117 runs sampled)'
'TRC-C get hit 1,000,000 x 2,268,161 ops/sec ±2.66% (116 runs sampled)'
'TRC-L get hit 1,000,000 x 2,633,628 ops/sec ±1.10% (118 runs sampled)'
'DWC get hit 1,000,000 x 2,217,895 ops/sec ±0.92% (117 runs sampled)'
'Clock set miss 100 x 8,758,950 ops/sec ±0.91% (117 runs sampled)'
'ISC set miss 100 x 9,296,804 ops/sec ±0.48% (121 runs sampled)'
'LRU set miss 100 x 10,147,622 ops/sec ±0.58% (121 runs sampled)'
'TRC-C set miss 100 x 9,839,048 ops/sec ±0.60% (120 runs sampled)'
'TRC-L set miss 100 x 9,289,720 ops/sec ±0.56% (124 runs sampled)'
'DWC set miss 100 x 8,512,914 ops/sec ±0.57% (122 runs sampled)'
'Clock set miss 1,000 x 8,809,238 ops/sec ±0.77% (118 runs sampled)'
'ISC set miss 1,000 x 8,247,771 ops/sec ±0.58% (122 runs sampled)'
'LRU set miss 1,000 x 8,830,509 ops/sec ±0.94% (117 runs sampled)'
'TRC-C set miss 1,000 x 8,829,582 ops/sec ±0.64% (119 runs sampled)'
'TRC-L set miss 1,000 x 8,086,730 ops/sec ±0.46% (121 runs sampled)'
'ISCCache get 100 100% x 27,154,321 ops/sec ±0.63% (123 runs sampled)'
'DWC set miss 1,000 x 7,560,890 ops/sec ±0.74% (118 runs sampled)'
'LRUCache get 100 100% x 23,510,090 ops/sec ±0.71% (123 runs sampled)'
'Clock set miss 10,000 x 9,502,782 ops/sec ±0.50% (122 runs sampled)'
'DW-Cache get 100 100% x 16,434,325 ops/sec ±0.29% (124 runs sampled)'
'ISC set miss 10,000 x 7,927,609 ops/sec ±0.40% (122 runs sampled)'
'Clock get 1,000 100% x 33,884,162 ops/sec ±0.22% (107 runs sampled)'
'LRU set miss 10,000 x 9,412,136 ops/sec ±0.55% (121 runs sampled)'
'ISCCache get 1,000 100% x 24,411,810 ops/sec ±0.26% (106 runs sampled)'
'TRC-C set miss 10,000 x 9,184,060 ops/sec ±0.45% (122 runs sampled)'
'LRUCache get 1,000 100% x 21,065,594 ops/sec ±0.16% (106 runs sampled)'
'TRC-L set miss 10,000 x 7,909,509 ops/sec ±0.97% (121 runs sampled)'
'DW-Cache get 1,000 100% x 15,385,560 ops/sec ±0.25% (107 runs sampled)'
'DWC set miss 10,000 x 7,428,354 ops/sec ±0.84% (121 runs sampled)'
'Clock get 10,000 100% x 36,391,602 ops/sec ±0.53% (107 runs sampled)'
'Clock set miss 100,000 x 5,883,863 ops/sec ±1.68% (116 runs sampled)'
'ISCCache get 10,000 100% x 22,475,190 ops/sec ±0.22% (107 runs sampled)'
'ISC set miss 100,000 x 4,739,615 ops/sec ±1.60% (115 runs sampled)'
'LRUCache get 10,000 100% x 15,406,949 ops/sec ±0.21% (107 runs sampled)'
'LRU set miss 100,000 x 6,086,843 ops/sec ±2.02% (115 runs sampled)'
'DW-Cache get 10,000 100% x 12,275,011 ops/sec ±0.50% (107 runs sampled)'
'TRC-C set miss 100,000 x 5,957,357 ops/sec ±1.99% (115 runs sampled)'
'Clock get 100,000 100% x 21,335,537 ops/sec ±0.19% (107 runs sampled)'
'TRC-L set miss 100,000 x 5,206,838 ops/sec ±2.42% (114 runs sampled)'
'ISCCache get 100,000 100% x 10,651,619 ops/sec ±0.54% (106 runs sampled)'
'DWC set miss 100,000 x 5,304,265 ops/sec ±2.26% (113 runs sampled)'
'LRUCache get 100,000 100% x 9,621,786 ops/sec ±1.05% (106 runs sampled)'
'Clock set miss 1,000,000 x 2,692,721 ops/sec ±4.15% (102 runs sampled)'
'DW-Cache get 100,000 100% x 8,171,402 ops/sec ±0.61% (106 runs sampled)'
'ISC set miss 1,000,000 x 2,320,462 ops/sec ±5.03% (100 runs sampled)'
'Clock get 1,000,000 100% x 13,408,228 ops/sec ±1.51% (105 runs sampled)'
'LRU set miss 1,000,000 x 2,687,115 ops/sec ±3.72% (107 runs sampled)'
'ISCCache get 1,000,000 100% x 3,819,976 ops/sec ±3.46% (96 runs sampled)'
'TRC-C set miss 1,000,000 x 2,943,312 ops/sec ±3.83% (106 runs sampled)'
'LRUCache get 1,000,000 100% x 2,411,793 ops/sec ±1.99% (100 runs sampled)'
'TRC-L set miss 1,000,000 x 2,690,687 ops/sec ±4.00% (102 runs sampled)'
'DW-Cache get 1,000,000 100% x 2,080,740 ops/sec ±1.66% (99 runs sampled)'
'DWC set miss 1,000,000 x 3,183,074 ops/sec ±4.12% (105 runs sampled)'
```

## API
Expand Down
12 changes: 6 additions & 6 deletions package.json
View file
Original file line number Diff line number Diff line change
Expand Up @@ -29,12 +29,12 @@
"LICENSE"
],
"dependencies": {
"spica": "0.0.768"
"spica": "0.0.782"
},
"devDependencies": {
"@types/mocha": "10.0.6",
"@types/power-assert": "1.5.12",
"@typescript-eslint/parser": "^6.17.0",
"@typescript-eslint/parser": "^7.0.1",
"babel-loader": "^9.1.3",
"babel-plugin-unassert": "^3.2.0",
"concurrently": "^8.2.2",
Expand All @@ -48,11 +48,11 @@
"karma-firefox-launcher": "^2.1.2",
"karma-mocha": "^2.0.1",
"karma-power-assert": "^1.0.0",
"mocha": "^10.2.0",
"npm-check-updates": "^16.14.12",
"mocha": "^10.3.0",
"npm-check-updates": "^16.14.15",
"ts-loader": "^9.5.1",
"typescript": "5.2.2",
"webpack": "^5.89.0",
"typescript": "5.3.3",
"webpack": "^5.90.2",
"webpack-cli": "^5.1.4",
"webpack-merge": "^5.10.0",
"zipfian-integer": "^1.0.1"
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