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upgpatch: spike 1.1.0-5
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Xeonacid authored and felixonmars committed Nov 21, 2024
1 parent bb64b1b commit 62d8f08
Showing 1 changed file with 7 additions and 10 deletions.
17 changes: 7 additions & 10 deletions spike/riscv64.patch
Original file line number Diff line number Diff line change
@@ -1,19 +1,16 @@
diff --git PKGBUILD PKGBUILD
index 30c0623..adb63dd 100644
index 1bd6efa..c65320b 100644
--- PKGBUILD
+++ PKGBUILD
@@ -18,6 +18,14 @@ makedepends=(git)
source=("git+https://github.com/riscv/riscv-isa-sim#commit=530af85d83781a3dae31a4ace84a573ec255fefa") # tag: v1.1.0
b2sums=(SKIP)
@@ -20,6 +20,11 @@

+prepare(){
+ cd riscv-isa-sim
prepare() {
sed -i '/#include <cstring>/a #include <cstdint>' riscv-isa-sim/fesvr/device.h
+
+ cd riscv-isa-sim
+ # Commits from https://github.com/riscv-software-src/riscv-isa-sim/pull/966
+ git cherry-pick -n e52327deeefb29908a822a9eb2f6fc5c87e968af
+ git cherry-pick -n dba7efaf9e2e8d5251820c8555a184f715bb4d46
+}
+
}
build() {
cd riscv-isa-sim
./configure --prefix=/usr

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