Merge pull request #173 from ferrous-systems/add-armv7r-too

Modify Armv8-R demo to also run on Armv7-R

example-code/build.sh

@@ -19,20 +19,21 @@ make clean
 popd
 # And the nRF52 examples
 pushd ./nrf52/bsp_demo
-cargo build
+cargo build --release
 cargo clean
 popd
 # And the qemu Aarch64 Armv8-A example
 pushd ./qemu-aarch64v8a
 criticalup install
 ./build.sh
-criticalup run cargo build
+criticalup run cargo build --release
 criticalup run cargo clean
 popd
-# And the qemu Aarch32 Armv8-R example
-pushd ./qemu-armv8r
+# And the qemu Aarch32 Armv8-R/Armv7-R example
+pushd ./qemu-aarch32v78r
 criticalup install
 ./build.sh
-criticalup run cargo build
+criticalup run cargo build --release
+criticalup run cargo build --target=armv7r-none-eabihf --release
 criticalup run cargo clean
 popd

example-code/qemu-aarch32v78r/.cargo/config.toml

@@ -0,0 +1,28 @@
+[target.armv8r-none-eabihf]
+rustflags = [
+    "-Clink-arg=-Tlinker.ld",
+    "-Ctarget-cpu=cortex-r52",
+]
+# Note, this requires QEMU 9 or higher
+runner = "qemu-system-arm -machine mps3-an536 -cpu cortex-r52 -semihosting -nographic -kernel"
+
+[target.armv7r-none-eabihf]
+rustflags = [
+    "-Clink-arg=-Tlinker.ld",
+    "-Ctarget-cpu=cortex-r5",
+]
+# This CPU is almost 100% Armv7-R compatible. Note: if we can find a machine
+# that supports Cortex-R5, but has an CMSDK UART at the same address at the
+# MPS3-AN536, we could use that instead.
+#
+# Note, this requires QEMU 9 or higher.
+runner = "qemu-system-arm -machine mps3-an536 -cpu cortex-r52 -semihosting -nographic -kernel"
+
+[build]
+target = ["armv8r-none-eabihf"]
+
+[source.crates-io]
+replace-with = "vendored-sources"
+
+[source.vendored-sources]
+directory = "vendor"

example-code/qemu-armv8r/Cargo.toml → example-code/qemu-aarch32v78r/Cargo.toml

@@ -1,5 +1,5 @@
 [package]
-name = "qemu-armv8r"
+name = "qemu-aarch32v78r"
 version = "0.1.0"
 edition = "2021"
 authors = ["Ferrous Systems"]

example-code/qemu-armv8r/README.md → example-code/qemu-aarch32v78r/README.md

@@ -11,7 +11,8 @@ This repository contains a small example application that can be built using the
 Ferrocene 24.05 is supported on *x86-64 Linux (glibc)*
 (`x86_64-unknown-linux-gnu`) as the host platform, and *Armv8-A bare-metal*
 (`aarch64-unknown-none`) as a cross-compilation target. This demo uses the
-early-access 'experimental' *Armv8-R bare-metal* (`armv8r-none-eabihf`) target.
+early-access 'experimental' *Aarch32 Armv8-R bare-metal* (`armv8r-none-eabihf`)
+and *Armv7-R bare-metal* (`armv7r-none-eabihf`) targets.
 
 You must first install Ferrocene by executing `criticalup install` inside this
 folder. This will require a valid CriticalUp token - please see the [CriticalUp
@@ -53,17 +54,21 @@ file configures the default target as `armv8r-none-eabihf`. It also sets up the
 linker arguments to ensure that [`./linker.ld`](./linker.ld) is used as the
 linker script.
 
+You can optionally pass `--target=armv7r-none-eabihf` to build an Aarch32
+Armv7-R binary instead. It will still run on an emulated Cortex-R52, but that
+CPU is almost 100% Armv7-R compatible.
+
 Before the build, `cargo` will compile and execute `build.rs`, which will copy
 the linker script to the `cargo` temporary output directory where the linker
 will look for it.
 
-The compiled outputs will go into `./target/armv8r-none-eabihf/<profile>`, where
-`<profile>` is `debug` or `release`. The binary is called `qemu-armv8r`, because
-that's the name given in the `Cargo.toml` file.
+The compiled outputs will go into `./target/armv?r-none-eabihf/<profile>`, where
+`?` is 7 or 8, and `<profile>` is `debug` or `release`. The binary is called
+`qemu-aarch32v78r`, because that's the name given in the `Cargo.toml` file.
 
 ```console
 $ criticalup run cargo run --release -bin no_heap
-   Compiling qemu-armv8r v0.1.0 (/Users/jonathan/work/qemu-armv8r)
+   Compiling qemu-aarch32v78r v0.1.0 (/Users/jonathan/work/qemu-aarch32v78r)
     Finished release [optimized] target(s) in 0.16s
      Running `qemu-system-arm -machine mps3-an536 -cpu cortex-r52 -semihosting -nographic -kernel target/armv8r-none-eabihf/release/no_heap`
 Hello, this is Rust!
@@ -99,7 +104,9 @@ by calling `rustc` directly. This script will:
 
 The outputs will go into `./target/production` and the binaries are called
 `no_heap` and `with_heap`. You can choose any suitable directory, but avoid
-clashing with anything you do using `cargo`.
+clashing with anything you do using `cargo`. The script uses
+`armv8r-none-eabihf` by default but you can easily change it to
+`armv7r-none-eabihf`.
 
 ```console
 $ ./build.sh

example-code/qemu-armv8r/build.sh → example-code/qemu-aarch32v78r/build.sh

@@ -61,7 +61,7 @@ echo Running rustc for lib...
 # ############################################################################
 "${RUSTC}" ${RUSTC_FLAGS} \
 	--crate-type=lib \
-	--crate-name=qemu_armv8r \
+	--crate-name=qemu_aarch32v78r \
 	--emit=dep-info,metadata,link \
 	--out-dir ${TARGET_DIR} \
 	-L ${TARGET_DIR} \
@@ -78,7 +78,7 @@ echo Running rustc for no_heap...
 	-Clink-arg=-Tlinker.ld \
 	--edition 2021 \
 	-L ${TARGET_DIR} \
-	--extern qemu_armv8r=${TARGET_DIR}/libqemu_armv8r.rlib \
+	--extern qemu_aarch32v78r=${TARGET_DIR}/libqemu_aarch32v78r.rlib \
 	-o ${NO_HEAP_OUTPUT_BINARY} \
 	src/bin/no_heap.rs
 echo Generating asm for no_heap...
@@ -93,7 +93,7 @@ echo Running rustc for with_heap...
 	-Clink-arg=-Tlinker.ld \
 	--edition 2021 \
 	-L ${TARGET_DIR} \
-	--extern qemu_armv8r=${TARGET_DIR}/libqemu_armv8r.rlib \
+	--extern qemu_aarch32v78r=${TARGET_DIR}/libqemu_aarch32v78r.rlib \
 	--extern embedded_alloc=${TARGET_DIR}/libembedded_alloc.rlib \
 	-o ${WITH_HEAP_OUTPUT_BINARY} \
 	src/bin/with_heap.rs

example-code/qemu-armv8r/criticalup.toml → example-code/qemu-aarch32v78r/criticalup.toml

@@ -9,4 +9,5 @@ packages = [
     "llvm-tools-${rustc-host}",
     "rust-src",
     "rust-std-armv8r-none-eabihf",
+    "rust-std-armv7r-none-eabihf",
 ]

example-code/qemu-armv8r/src/bin/global_uart.rs → example-code/qemu-aarch32v78r/src/bin/global_uart.rs

@@ -9,7 +9,7 @@
 
 use core::{cell::RefCell, fmt::Write};
 use critical_section::Mutex;
-use qemu_armv8r::cmsdk_uart::Uart;
+use qemu_aarch32v78r::cmsdk_uart::Uart;
 
 /// The clock speed of the peripheral subsystem on an SSE-300 SoC an on MPS3 board.
 ///

example-code/qemu-armv8r/src/bin/no_heap.rs → example-code/qemu-aarch32v78r/src/bin/no_heap.rs

@@ -8,7 +8,7 @@
 #![no_main]
 
 use core::fmt::Write;
-use qemu_armv8r::cmsdk_uart;
+use qemu_aarch32v78r::cmsdk_uart;
 
 /// The clock speed of the peripheral subsystem on an SSE-300 SoC an on MPS3 board.
 ///

example-code/qemu-armv8r/src/bin/with_heap.rs → example-code/qemu-aarch32v78r/src/bin/with_heap.rs

@@ -11,7 +11,7 @@ extern crate alloc;
 
 use core::{fmt::Write, ptr::addr_of_mut};
 use embedded_alloc::Heap;
-use qemu_armv8r::cmsdk_uart;
+use qemu_aarch32v78r::cmsdk_uart;
 
 #[global_allocator]
 static HEAP: Heap = Heap::empty();

example-code/qemu-armv8r/src/lib.rs → example-code/qemu-aarch32v78r/src/lib.rs

@@ -10,11 +10,12 @@ core::arch::global_asm!(
 .global _start
 .code 32
 .align 0
+// Work around https://github.com/rust-lang/rust/issues/127269
+.fpu vfp3-d16
 
 _start:
     // Set stack pointer
-    ldr r3, =stack_top
-    mov sp, r3
+    ldr sp, =stack_top
     // Allow VFP coprocessor access
     mrc p15, 0, r0, c1, c0, 2
     orr r0, r0, #0xF00000