LPC55xx: DMA-based SWD implementation.

flit · Jan 26, 2021 · bea76ce · bea76ce
1 parent ef8cad9
commit bea76ce
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Showing 6 changed files with 778 additions and 0 deletions.
diff --git a/source/hic_hal/nxp/lpc55xx/DAP_config.h b/source/hic_hal/nxp/lpc55xx/DAP_config.h
@@ -24,6 +24,7 @@
 
 #include "IO_Config.h"
 #include "fsl_iocon.h"
+#include "swd_dma.h"
 
 //**************************************************************************************************
 /**
@@ -549,6 +550,9 @@ __STATIC_INLINE void DAP_SETUP(void)
                                     | PIN_TDO_SWO_MASK
                                     | PIN_TDI_MASK
                                     | PIN_RESET_MASK;
+
+    // Setup DMA-based SWD.
+    swd_dma_init();
 }
 
 /** Reset Target Device with custom specific I/O pin or command sequence.

diff --git a/source/hic_hal/nxp/lpc55xx/daplink_addr.h b/source/hic_hal/nxp/lpc55xx/daplink_addr.h
@@ -66,6 +66,10 @@
 #define DAPLINK_SECTOR_SIZE             0x00000200
 #define DAPLINK_MIN_WRITE_SIZE          0x00000200
 
+/* DMA RAM - SRAM4 */
+#define DAPLINK_DMA_RAM_START           0x20040000
+#define DAPLINK_DMA_RAM_SIZE            0x00004000
+
 /* USB RAM */
 #define DAPLINK_USB_RAM_START           0x40100000
 #define DAPLINK_USB_RAM_SIZE            0x00004000

diff --git a/source/hic_hal/nxp/lpc55xx/gcc/lpc55xx.ld b/source/hic_hal/nxp/lpc55xx/gcc/lpc55xx.ld
@@ -37,6 +37,7 @@ MEMORY
   m_cfgrom              (RW)  : ORIGIN = DAPLINK_ROM_CONFIG_USER_START, LENGTH = DAPLINK_ROM_CONFIG_USER_SIZE
   m_data                (RW)  : ORIGIN = DAPLINK_RAM_APP_START, LENGTH = DAPLINK_RAM_APP_SIZE
   m_cfgram              (RW)  : ORIGIN = DAPLINK_RAM_SHARED_START, LENGTH = DAPLINK_RAM_SHARED_SIZE
+  m_dma_ram             (RW)  : ORIGIN = DAPLINK_DMA_RAM_START, LENGTH = DAPLINK_DMA_RAM_SIZE
   m_usb_ram             (RW)  : ORIGIN = DAPLINK_USB_RAM_START, LENGTH = DAPLINK_USB_RAM_SIZE
 }
 
@@ -212,6 +213,13 @@ SECTIONS
     *(cfgram)
   } > m_cfgram
 
+  .dmaram (NOLOAD) :
+  {
+    . = ALIGN(4);
+    *(.dmaram)
+    . = ALIGN(4);
+  } > m_dma_ram
+
   .usbram (NOLOAD) :
   {
     . = ALIGN(4);

diff --git a/source/hic_hal/nxp/lpc55xx/hic_init.c b/source/hic_hal/nxp/lpc55xx/hic_init.c
@@ -30,6 +30,7 @@
 #include "util.h"
 #include "flash_hal.h"
 #include "pin_mux.h"
+#include "swd_dma.h"
 
 #define FLASH_CMD_BLANK_CHECK (0x5)
 
@@ -205,6 +206,9 @@ void hic_enable_usb_clocks(void)
 
     // Init PHY.
     USB_EhciPhyInit(kUSB_ControllerLpcIp3511Hs0, BOARD_XTAL0_CLK_HZ, NULL);
+
+    // Let the SWD DMA implementation update its clock.
+    swd_dma_update_clock();
 }
 
 void hic_power_target(void)