oc24: Add missing co-speaker

content/orconf/2024/talks.csv

@@ -34,5 +34,5 @@ The background of FuseSoC has been presented several times over the years, so th
 ,,Normal,Porting of Proprietary PDK to Digital Open-Source EDA Tools,Tomasz Hemperek,,,"Open-source tools for ASIC design are gaining momentum due to their cost-effectiveness, customizability, and reliability. These tools have proven their value through multiple successful designs in recent years. This talk will present our experience in successfully porting a proprietary 110nm Process Design Kit (PDK) to open-source EDA tools such as Yosys and OpenRoad. We will discuss both the successes and challenges encountered during this process, using the prototype Gbit serial data link as a case study."
 ,,Normal,Teaching Analog IC Design using Open Source Tools,Ted Johansson,,,"EU and USA Chips Act programs have regained the focus on fabrication of semiconductors, new devices, circuit design, and the supply chains. In the next couple of years, huge amounts of money, shared between government and industry, will be spent on rebuilding the semiconductor industry in Europe and USA. However, during the last 25 years, this area has not attracted the students. We need to educate a new generation of engineers and researchers on semiconductors and circuit design. Analog/RF circuit design is usually not very complex, but often requires knowledge of actual device physics and parameters. It also requires many simulation to find good circuit solutions and robust designs. Open-source tools for parts of IC design flows have been available for a long time, but only lately, open process information (process design kits, PDKs) has been made available, which make fully open-source design flows for circuit design and commercial foundry fabrication possible. But how well suited for exploring and teaching the principles of analog/RF IC design are open-source tools and PDKs compared to commercial tools and closed PDKs? And can they be used for prototype chips in research projects? In the presentation, I will describe how we created a PhD course (also suitable for master programs) on analog IC design, addressing the design chain, tools, and everything you need to know to design and have chips fabricated at a foundry using only open-source tools and PDKs. A comparison with the commercial tools currently used in education and industry will also be made."
 ,,Normal,Buckets of Coverage,Stuart Alldred,,,"Bucket is a python-based functional coverage tool designed to work easily with cocotb(/Forastero). It allows for the easy creation of multiple nested covergroups and coverpoints with a straight forward sampling mechanism. Each coverpoint is a cross of one or more axes, with the ability to modify target hits, illegal or ignore status for each bucket. The data to be covered can be sampled directly from the DUT, higher levels of abstraction (such as entire CPU pipelines), or even parsing of logs/test output. Bucket is being actively developed and used by Vypercore for our own IP. It is fully open source and available at github.com/VyperCore/bucket, where you can find further documentation and examples."
-,,Normal,BenchBot: Automated OSVVM Testbench Template Generator for VHDL DUTs,Adruth Vasudevan Srinivasan,,,"BenchBot is an open-source Python based app developed to automate the generation of OSVVM-compliant testbenches for VHDL designs. It utilizes YAML configuration files to define testbench parameters, enabling users to quickly produce tailored test environments for their DUTs. Main goal of this bot is to provide a ready-to-use OSVMM compliant testbench for a given VHDL DUT with popular elements such as clock generator, reset generator, main stimulus place holder, a watchdog etc. It also paves way to distributed test development by leveraging on modular testbench architecture using OSVMM framework. In this paper, we share our experience of using BenchBot on various open-source VHDL designs available online for the community, ensuring its reliability and versatility across different use cases. Along the way, we found a few unsupported constructs and added enhancements to the bot. This bot streamlines the process of creating standardized testbenches, making integrating it into existing VHDL development workflows easier."
+,,Normal,BenchBot: Automated OSVVM Testbench Template Generator for VHDL DUTs,Adruth Vasudevan Srinivasan / Arya Sharma,,,"BenchBot is an open-source Python based app developed to automate the generation of OSVVM-compliant testbenches for VHDL designs. It utilizes YAML configuration files to define testbench parameters, enabling users to quickly produce tailored test environments for their DUTs. Main goal of this bot is to provide a ready-to-use OSVMM compliant testbench for a given VHDL DUT with popular elements such as clock generator, reset generator, main stimulus place holder, a watchdog etc. It also paves way to distributed test development by leveraging on modular testbench architecture using OSVMM framework. In this paper, we share our experience of using BenchBot on various open-source VHDL designs available online for the community, ensuring its reliability and versatility across different use cases. Along the way, we found a few unsupported constructs and added enhancements to the bot. This bot streamlines the process of creating standardized testbenches, making integrating it into existing VHDL development workflows easier."
 ,,Normal,SoCESS? - Adventures deploying (digital design) Open Source assets into Curriculum,John Goodenough,,,"The many efforts in the open source community have produced IP and tool assets that can no be deployed at scale into Curriculum. At the University of Sheffield we have begun a multi year curriculum transformation within the school of Electronic and Electrical Engineering. We will outline our plans , discuss delivery constraints and report on experiences to date deploying at moderate cohort scale, this will focus on digital SoC design using Risc-V. The non technical experiences should transfer to other methodology and flow areas. We aim to catalyse the community in thinking more deeply about user needs for in academic teaching and to promote further collaboration and sharing of ideas"